Fundamentals of Logic Design 7th Edition

I: INTRODUCTION The text, Fundamentals of Logic Design,7th edition, has been designed so that it can be used either for a standard lecture course or for a self-paced course. The text is divided into 20 study units in such a way that the average study time for each unit is

Unit 2 Solutions 17 (A + B + C + D) (A + B + C + E) (A + B + C + F) = A + B + C + DEF Apply second Distributive Law twice See FLD p. 731 for solution. 2.1 Unit 2 Problem Solutions 2.2 (a) In both cases, if

Unit 3 Solutions 23 3.10 (a) 3.10 (b) (A ⊕ BC) + BD + ACD = A'BC + A(BC)' + BD + ACD = A'BC + A (B' + C') + BD + ACD = A'BC + AB' + AC' + BD + ACD = A'BC + AB' + AC'

31 Unit 4 Solutions x y z0 z1 z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0

Unit 5 Solutions 41 Unit 5 Problem Solutions 5.3 (a) a b c 0 1 00 01 11 10 1 1 1 f1 = a'c' + a b'c + b c' 01 11 10 1 1 1 1 f3 = r' + t' 01 11 10 1 1 1 0 1 1 f4 = x'z + y + x z' 01 11 10 1 1 f2 = d'e' + d'f + e'f ' ' 1 5.3 (b) 5.3 (c) r s t 0 1 00 1 1 5.3 (d)

57 Unit 6 Solutions Unit 6 Problem Solutions 100011, 5 0-01 a'c'd 501011, 9 -001 b'c'd 910015, 7 01-1 a'bd 12 11009, 11 10-1 ab'd 7011112, 14 11-0 abd' 11 10117, 15 -111 bcd 14 111011, 15 1-11 acd 15 111114, 15 111- abc Prime implicants: a'c'd, b'c'd, a'bd, ab'd, abd', bcd, acd, abc 501018, 10 10-0 ab'd' 601103, 7 0-11 10 10105,

Unit 7 Solutions © 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part. Unit 7 Problem Solutions a b c d 00 01 11 10 00 01 11 10 0 0 1 1 1 0 0 0 f = (a'+ b') (a + b ) (a + c +

Unit 8 Design Solutions © 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part. Problems 8.A through 8.S are combinational logic design problems using NAND and NOR gates. Problems 8.A through 8.R are of approximately

91 Unit 8 Solutions Unit 8 Problem Solutions 8.1 8.2 (a) (cont.) Static 1-hazards: 1101↔1111 and 0100↔0101 15 V Z 0 5 10 20 25 30 35 40 t (ns) 01 11 10 1 1 1 1 1 1 F = A'C'D' + A C + B C'D 8.2 (a) Y X WA B C D 00 01 11 10 00 1 1 A B C D 00 01 11 10 00 01 11 10 0 0 0 0 F = (A +

Unit 9 Solutions 97 Unit 9 Problem Solutions 9.1 See FLD p. 741 for solution. 9.2 See FLD p. 741 for solution. 9.3 See FLD p. 742 for solution. 9.4 See FLD p. 742 and Figure 4-4 on FLD p.109. 9.5 y0 y1 y2 y3 a b c 0 0 0 0 0

© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part. NAME PASSWORD DATE (signature) READINESS TEST - UNIT 1 - FORM A Please answer the following questions carefully without any reference to

113 Unit 10 Solutions Unit 10 Problem Solutions 10.1 See FLD p. 747 for solution. 10.2 See FLD p. 747 for solution. 10.3 See FLD p. 748 for solution 10.4 See FLD p. 748 for solution. 10.5 See FLD p. 748 for solution. Notes: The function vec2int is found in bit_pack, which is in the

© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part. Unit 10 Design Solutions 10.A I0 I1 I2 I3 F B A B architecture eqn of mux2_1 is begin z <= (i0 and not sel) or (i1 and sel); -- alt: z <= i1 when sel

Unit 11 Solutions © 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part. Unit 11 Problem Solutions 11.1 Z responds to X and to Y after 10 ns; Y responds to Z after 5 ns. See FLD

297 Unit 12 Design Solutions Solutions to Unit 12 Design and Simulation Problems Problem 12.10 is a simulation exercise where students are required to design and simulate a counter. The problem has 14 parts of equal difculty, so that different students can be assigned different parts. We ask students to do

125 Unit 12 Solutions Unit 12 Problem Solutions 12.1 Consider 3 × Y = Y + Y + Y, that is, we need to add Y to itself 3 times. First, clear the accumulator before the first rising clock edge so that the X-register is 000000. Let the Ad pulse be

Unit 13 Solutions © 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part. Unit 13 Problem Solutions Z depends on the input X, so this is a Mealy machine. Because there are more than 2 state

157 Unit 14 Solutions Unit 14 Problem Solutions 14.4 Typical input and output sequences: X = 0 1 0 0 0 0 0 1 0 1 0 1 1 ... Z = (0) 0 0 0 0 0 0 0 1 1 1 ... (output remains 1) X =

Unit 15 Solutions 189 15.25 (c) (cont.) 00 01 11 10 00 01 11 10 X 1 X X X 1 X X Q1+ = Q2 + XQ1' 11 10 X 0 X X X 0 X X Q2+ = XQ1Q3' 11 10 X 0 X X X 1 X X Q3+ = X'Q1 + X Q1'Q3 + Q1Q3' 11 10 X 1 X X Z = Q1' 0 0 0 0 1 1 0 0 X Q1 Q2 Q300 01 11 10 00 01 0 0 0 0 0 0 1 0 X Q1 Q2 Q300 01 11 10 00 01 0 0 1 1 0 1 1 0 X Q1 Q2 Q3 Q1 Q2 Q30 1 00 01 1 1 0 0 00 01 11 10 00 01 11 10 X 1 X X X 1 X X J1 = Q2 + X 11 10 X X X X X X X X J2 = XQ1Q3' 11 10 X X X X X X X X K1 = 1 11 10 X 1 X X X 1 X X K2

Unit 15 Solutions 177 b c-e c d e-h e-a c-h e-a e h-f f i-e h-g i-e f-g g e-h e-b c-h e-b a-b h c-i d-h c-i f-d c-e g-d i e-f e-b c-f b-e h-f a-b h-f a b c d e f g h Unit 15 Problem Solutions 15.1 (a) Reduced state table: State Next State X = 0 X = 1 Output X = 0 X = 1 A A C1 0 B C F0 0 C B A0 0 F

Unit 16 Design Solutions 303 Solutions to Unit 16 Design and Simulation Problems Problems 16.1 through 16.14 are Mealy sequential circuit design and simulation problems. These problems are of approximately equal difficulty so that different students can be assigned different problems. In this exercise, students first complete their designs using gates and

201 Unit 16 Solutions i i a xi ' i+1 a S1 S1 S20 S2 S2 S30 S3 S3 S21 I: (1, 3) II: (0, 1) (1, 2) (2, 3)2x 01 11 10 0 1 1 1 0 0 a i+1 = xi'ai + xi ai' ai+1 = xiai ' + xi 'ai x a i ' i x ai i+1 b i b' i+1 b S110 10 01 0 S201 01 11 0 S311 11 01 1 z = an+1bn+1 bi+1 =

313 Unit 17 Design Solutions Solutions to Unit 17 Simulation and Lab Problems Problems 17.A through 17.M are relatively easy VHDL problems that use a register, counter, or other clocked device. We ask students to write VHDL code for their assigned problem, and then simulate, test, and debug their code. We

Unit 17 Solutions © 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part. See FLD p. 773 for solutions. 17.6 (a), (b) X1 CLK CLK 2 X 4 ROM DQ DQ Q1 Q2 Q1+ Q2+ 4 X2 Z1 Z2 Unit 17 Problem Solutions 17.1 See FLD p. 770 for solution. 17.2 See FLD

229 Unit 18 Solutions Unit 18 Problem Solutions 18.3 See FLD p. 775 for circuit. Notice that the Q output of the ip-op is bin , while the D input is bout . 18.4 S1 S5 St 0 ShSh Sh St'0St Sh S2 S4 S3 Sh 18.7 (a) Overow occurs only on division by 0, so V = y0 'y1 'y2 'y3 'y4 ' = (y0 + y1

Unit 19 Solutions 245 Unit 19 Problem Solutions 19.1 See FLD p. 777 for solution. 19.2 See FLD p. 777 for solution. 19.5 See FLD p. 778 for solution. 19.6 See FLD p. 779 for solution. 19.7 See FLD p. 779 for solution. 19.8 See FLD p. 779 for solution. 19.9 See FLD p. 779-780 for solution.

257 Unit 20 Solutions Unit 20 Problem Solutions 20.1 See FLD p. 781 for solution. 20.2 See FLD p. 781-782 for solution. 20.3 Replace line 12 with: signal State, Nextstate: integer range 0 to 5; Replace lines 27 - 33 with: when 1 | 2 | 3 | 4 => if M = '1' then

Unit 20 Design Solutions © 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part. Solutions to Unit 20 Lab Design Problems As a final lab assignment in our course, we ask students to solve one of the

336 Unit 20 Design Solutions 20N without counter St Control 6 bit Adder Clk M Ld2 Multiplicand[5:0] 6 InBus 0 done Rst 13 product 16 3 "000" Clk Accumulator[13:0] Multiplier[6:0] Ld1 7 7 Sh Ad 20.N S1 S0 St'0 St Ld1 -Ld2 M' Sh MAd 20N without counter M' Sh M' Sh M' Sh MAd MAd - Sh - Sh - Sh - Sh S7 S13 S8 S9 S10 S12 M' Sh MAd S11 S5 S6 S4 M' Sh MAd - Sh -- 20N multiplier 6 x 7 (no counter) (cont.) begin -- hex: hex_display port map(product, hex_out, int_clk, -- e0, e1, e2, e3); product <= “000” & acc(12 downto 0); addout