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Unit 17 Design Solutions
17.K library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
signal Qint : std_logic_vector (3 downto 0);
begin
Q <= Qint;
process(CLK, ClrN)
begin
if ClrN = ‘0’ then Qint <= “0000”;
Command sequence:
force clk 1 0, 0 100 -repeat 200
Test data:
– set ClrN = 1 for 3.5 clock cycles
= 0 for the next half clock cycle
= 1 for the rest of the test
– set Sh = 0 for 1 clock cycle
= 1 for the next 5 clock cycles
= 0 for the rest of the test
0ns 200ns 400ns 600ns 800ns 1000ns 1200ns 1400ns 1600ns
Clk
ClrN
Sh
SI
L
D
Q
Signal
5
U5 A D 0 8 C E 5
17.L library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sregister is
begin
if ClrN =’0′ then Acc <= “00000000”;
elsif CLK’event and CLK = ‘1’ then
if Ad = ‘1’ then Acc <= Acc + D;
elsif Sh = ‘1’ then Acc <= Acc(6 downto 0)&’0′;
else Acc <= Acc; end if;
Command sequence:
force CLK 0 0, 1 100 -repeat 200
force ClrN 1 0, 0 25, 1 50
– set Sh = 0 for 2 clock cycles
= 1 for 2 clock cycles
= 0 for the rest of the test
8-bit accumulator
CLK
Sh
Q(5) Q(4) Q(3) Q(2) Q(1) Q(0)
Ad
ClrN
Q(7) Q(6)