Chapter 17 Add Asynchronous Reset Input 2 Simulate The

subject Type Homework Help
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subject Authors Jr.Charles H. Roth, Larry L Kinney

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313
Unit 17 Design Solutions
Solutions to Unit 17 Simulation and Lab Problems
Problems 17.A through 17.M are relatively easy VHDL problems that use a register, counter, or other clocked device.
We ask students to write VHDL code for their assigned problem, and then simulate, test, and debug their code. We
have provided appropriate test sequences for each of these problems in the solutions that follow. We ask students to
turn in simulation waveforms that demonstrate the operation of their code.
In addition to solving one of the above problems, we ask students to perform the following lab exercise:
(1) Write behavioral VHDL code that implements the state machine that you designed in Unit 16 (one of
problems 16.1 through 16.14). Use a case statement to represent the state table as illustrated in FLD
Figure 17-17. Use two processes – one for the combinational logic and one for the state register. Add an
17.A library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Lab17A is
port (CLK, ClrN, SI : in std_logic;
SO : out std_logic);
begin
if ClrN='0' then Q <= "00000000";
elsif CLK' event and CLK='1' then
Q <= SI & Q(7 downto 1); end if;
end process;
end Behavioral;
Command sequence:
force CLK 0 0, 1 100 -repeat 200
Test data:
- reset
- set Si = 0 1 0 0 1 1 0 0 0 0 0 0
0ns 400ns 800ns 1200ns 1600ns 2000ns 2400ns 2800ns
CLK
ClrN
Signal
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Unit 17 Design Solutions
17.B
4-bit Counter
PreN
En
C
Q(3) Q(2) Q(1) Q(0) library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Lab17B is
port (CLK, PreN, En, C : in std_logic;
begin
if PreN = '0' then Q <= "1111";
elsif CLK'event and CLK = '1' then
if En = '0' then Q <= Q;
Command sequence:
force CLK 0 0, 1 100 -repeat 200
force PreN 1 0, 0 25, 1 50
0ns 400ns 800ns 1200ns 1600ns 2000ns 2400ns 2800ns
CLK
PreN
Signal
17.C library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Command sequence:
force CLK 0 0, 1 100 -repeat 200
force ClrN 1 0, 0 25, 1 50
run 2000ns
Test data:
- Counter sequence: 000, 010, 100, 110, 001, 011,
101, 111, 000 ...
signal Q, ROM_out, Index, D : std_logic_vector(0 to 2);
begin
Index <= Q;
ROM_out <= ROM1(conv_integer(Index));
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Unit 17 Design Solutions
17.D
1*2*
0
reset when F=0
reset when F=0
*CLKout = 1 in states
1 and 2
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Lab17D is
port (CLK, F : in std_logic;
CLKout : out std_logic);
end Lab17D;
architecture Behavioral of Lab17D is
if Rst = '1' then count <= 0;
elsif count = 2 then count <= 0;
else count <= count + 1; end if;
end if;
end process;
end Behavioral;
Command sequence:
force CLK 0 0, 1 100 -repeat 200
force F 0 0, 1 1000, 0 2400
run 3600ns
- reset
- set F = 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0
Counter
CLK
CLKout
17.E library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
begin
RSO <= qint(0);
LSO <= qint(7);
process(ClrN, Clk)
begin
if ClrN='0' then qint <= "00000000";
elsif Clk' event and Clk='1' then
if En='1' and R='1' then qint <= RSI&qint(7 downto 1);
Command sequence:
force Clk 0 0, 1 100 -repeat 200
- set RSI = 1; LSI = 0
- set En = 0 for 2 clock cycles
- set En = 1 for the rest of the test
- Shift Right 9x
- Shift Left 9x
8-bit serial-in, serial out
right-left shift register
LSO
RSI
RSO
LSI
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Unit 17 Design Solutions
17.F library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Lab17F is
port (Clk, ClrN, R, L, RSI, LSI : in std_logic;
RSO, LSO: out std_logic);
end Lab17F;
architecture Behavioral of Lab17F is
signal Q: std_logic_vector(5 downto 0);
end Behavioral;
Test data:
- reset
- set LSI = 1; RSI = 1
6-bit serial-in, serial out
right-left shift register
Clk
LSO
RSI
RSO
LSI
L R ClrN
0ns 200ns 400ns 600ns 800ns 1000ns
Clk
ClrN
R
Signal
17.G library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity acc_6bit is
port (CLK, ClrN, Ad, CI : in std_logic;
D : in std_logic_vector(5 downto 0);
end Behavioral;
6-bit register
CLK
Ad
ClrN
Accout
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Unit 17 Design Solutions
Command sequence:
force CLK 0 0, 1 100 -repeat 200
force ClrN 1 0, 0 25, 1 50
force Ad 1
0ns 200ns 400ns 600ns 800ns
CLK
ClrN
Signal
17.G
(cont.)
17.H
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port (CLK, ClrN, En, U : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counter;
architecture Behavioral of counter is
signal W: std_logic_vector(3 downto 0):="0000";
begin
Test data:
- reset
4-bit up-down counter
CLK
En
U
Q(3) Q(2) Q(1) Q(0)
ClrN
0ns 200ns 400ns 600ns 800ns 1000ns 1200ns 1400ns 1600ns 1800ns
Clk
Clr
En
U
Q
Signal
01 2 3 4 3 2 1 0 F E
17.I architecture Behavioral of counter is
signal W : std_logic_vector(5 downto 0):="000000";
begin
Q <= W;
En
Q(3)Q(4)Q(5) Q(2) Q(1) Q(0)
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Unit 17 Design Solutions
0ns 200ns 400ns 600ns 800ns 1000ns 1200ns
CLK
Signal
17.I
(cont.)
17.J
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL
entity Lab17J is
port ( Memin : in std_logic_vector(5 downto 0);
Clk, Ld : in std_logic;
Sel : in std_logic_vector(1 downto 0);
Memout : out std_logic_vector(5 downto 0));
Test data:
- set Memin = 100001, Ld = 1, Sel = 11
- set Memin = 000000, Ld = 0, Sel = 11
- set Ld = 1
- set Memin = 010010, 001100, 000111
while Sel = 10, 01, 00
- set Ld = 0, Memin = 111111
Clk
Ld
Ld
Register a
Register b
2-to-4
decoder
Ld
Ld
6
6
6
6
6
Memout
6
Memin 6
2
Sel
--Code for tri-state buffers
Memout <= Reg_a when Sel_a = ‘1’ else "ZZZZZZ";
Memout <= Reg_b when Sel_b = ‘1’ else "ZZZZZZ";
Memout <= Reg_c when Sel_c = ‘1’ else "ZZZZZZ";
Memout <= Reg_d when Sel_d = ‘1’ else "ZZZZZZ";
--Code for Registers
process(clk)
begin
if Clk’event and Clk = ‘1’ then
0ns 200ns 400ns 600ns 800ns 1000ns 1200ns 1400ns 1600ns
Clk
Sel
Ld
Memin
Signal
32 1 0 3 2 1 0
21 00 12 0C 07 3F
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Unit 17 Design Solutions
17.K library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
signal Qint : std_logic_vector (3 downto 0);
begin
Q <= Qint;
process(CLK, ClrN)
begin
if ClrN = '0' then Qint <= "0000";
Command sequence:
force clk 1 0, 0 100 -repeat 200
Test data:
- set ClrN = 1 for 3.5 clock cycles
= 0 for the next half clock cycle
= 1 for the rest of the test
- set Sh = 0 for 1 clock cycle
= 1 for the next 5 clock cycles
= 0 for the rest of the test
0ns 200ns 400ns 600ns 800ns 1000ns 1200ns 1400ns 1600ns
Clk
ClrN
Sh
SI
L
D
Q
Signal
5
U5 A D 0 8 C E 5
17.L library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sregister is
begin
if ClrN ='0' then Acc <= "00000000";
elsif CLK'event and CLK = '1' then
if Ad = '1' then Acc <= Acc + D;
elsif Sh = '1' then Acc <= Acc(6 downto 0)&'0';
else Acc <= Acc; end if;
Command sequence:
force CLK 0 0, 1 100 -repeat 200
force ClrN 1 0, 0 25, 1 50
- set Sh = 0 for 2 clock cycles
= 1 for 2 clock cycles
= 0 for the rest of the test
8-bit accumulator
CLK
Sh
Q(5) Q(4) Q(3) Q(2) Q(1) Q(0)
Ad
ClrN
Q(7) Q(6)
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Unit 17 Design Solutions
17.M library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
begin
if CLK'event and CLK='1' then
if (A and B)='1' then Acc <= Acc-D;
elsif (A and not B)='1' then Acc <= D;
elsif (not A and B)='1' then
Acc <= '0'&Acc(7 downto 1); end if;
end if;
Command sequence:
force CLK 0 0, 1 100 -repeat 200
force D 11100010
force A 1
force B 0
= 11 for the rest of the test
A
Q(5) Q(4) Q(3) Q(2) Q(1) Q(0)
Q(7) Q(6)
17.L
(cont.) 0ns 200ns 400ns 600ns 800ns 1000ns 1200ns
CLK
Signal

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