# Chapter 20 We ask our students to follow the procedure given

Type Homework Help
Pages 9
Words 251
Textbook Fundamentals of Logic Design 7th Edition
Authors Jr.Charles H. Roth, Larry L Kinney

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336
Unit 20 Design Solutions
20N without counter
Clk
Accumulator[13:0]
Multiplier[6:0]
Ld1
7
7
Sh
20.N
S1
S0
St'0
St Ld1
-Ld2
- Sh
-done
M'
Sh
S2
S14
- Sh
S15 S16
S3
-- 20N multiplier 6 x 7 (no counter)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity multiplier is
port (Clk: in std_logic;
St: in std_logic;
Rst: in std_logic;
done: out std_logic;
InBus: in std_logic_vector(7 downto 0);
int_clk: in std_logic;
No Counter:
when 1 =>
Ld2 <= ‘1’; nextstate <= 2;
when 2|4|6|8|10|12|14 =>
if M = ‘1’ then Ad <= ‘1’; nextstate <= state+1;
else Sh <= ‘1’; nextstate <= state +2; end if;
when 3|5|7|9|11|13|15 =>
Sh <= ‘1’; nextstate <= state + 1;
when 16 =>
done <= ‘1’; nextstate <= 0;
end case;
end process;
process(Clk,Rst)
337
Unit 20 Design Solutions
20N with counter
Clk
Accumulator[13:0]
Multiplier[6:0]
7Sh
Counter
k
Ld1
7
20.N
(cont.)
With Counter:
St'0
20N with counter
S0
St Ld1
-done
k'M'
Sh
-- 20N with counter
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity multiplier is
port (Clk: in std_logic;
architecture control1 of multiplier is
signal state, nextstate : integer range 0 to 4;
signal Mcand: std_logic_vector(5 downto 0);
-- 20N with counter (cont.)
begin
-- hex: hex_display port map(product, hex_out, int_Clk,
-- e0, e1, e2 ,e3);
product <= “000” & acc(12 downto 0);
when 1 =>
Ld2 <= ‘1’; nextstate <= 2;
when 2 =>
if M = ‘1’ then Ad <= ‘1’; nextstate <=3;
elsif k = ‘0’ then Sh <= ‘1’; nextstate <=2;
else Sh <= ‘1’; nextstate <= 4; end if;
when 3 =>
if k = ‘0’ then Sh <= ‘1’; nextstate <= 2;
else Sh <= ‘1’; nextstate <= 4; end if;
when 4 =>
if Ld1 = ‘1’ then Mcand <= InBus(5 downto 0); end if;
if Ld2 = ‘1’ then
acc(6 downto 0) <= InBus(6 downto 0); end if;
if Ad = ‘1’ then acc(13 downto 7) <= addout; end if;
338
Unit 20 Design Solutions
20O without counter
done
Clk
Accumulator[13:0]
Multiplier[5:0]
Ld1
7
6
Sh
20.O No Counter:
S1
S0
St'0
St Ld1
-Ld2
-done
M'
S7
S13 S14
- Sh
-- 20O without counter
library IEEE;
use IEEE.STD_LOGIC_1164.all;
else nextstate <=0; end if;
when 1 =>
Ld2 <= ‘1’; nextstate <= 2;
when 2|4|6|8|10|12 =>
if M = ‘1’ then Ad <= ‘1’; nextstate <=state+1;
else Sh <= ‘1’; nextstate <= state +2; end if;
339
Unit 20 Design Solutions
20.O
(cont.)
20O with counter
Accumulator[13:0]
Multiplier[5:0]
7
Sh
Counter
Clk
Ld1
6
With Counter:
St'0
S0
St Ld1
-done
-- 20O with counter
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity multiplier is
port (Clk: in std_logic;
St: in std_logic;
architecture control1 of multiplier is
signal state, nextstate: integer range 0 to 4;
signal Mcand: std_logic_vector(6 downto 0);
-- 20O with counter (cont.)
begin
-- hex: hex_display port map(product, hex_out, int_clk,
-- e0, e1, e2, e3);
product <= “000” & acc(12 downto 0);
addout <= (‘0’ & acc(12 downto 6)) + Mcand;
when 2 =>
if M = ‘1’ then Ad <= ‘1’; nextstate <=3;
elsif k = ‘0’ then Sh <= ‘1’; nextstate <=2;
else Sh <= ‘1’; nextstate <= 4; end if;
when 3 =>
if k = ‘0’ then Sh <= ‘1’; nextstate <= 2;
else Sh <= ‘1’; nextstate <= 4; end if;
when 4 =>
if Ld1 = ‘1’ then Mcand <= InBus(6 downto 0); end if;
if Ld2 = ‘1’ then
acc(5 downto 0) <= InBus (5 downto 0); end if;
if Ad = ‘1’ then acc(13 downto 6) <= addout; end if;
340
Unit 20 Design Solutions
20.P
20P without counter
St
done
Clk
8
5
8
No Counter:
S1
S0
St'0
St Ld1
-Ld2
-done
M'
- Sh
S12
S11
-- 20P without counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity lab20PwithoutCounter is
architecture behavioral of lab20PwithoutCounter is
signal state, nextstate: integer range 0 to 12;
signal mcand: std_logic_vector( 7 downto 0 );
signal acc: std_logic_vector( 13 downto 0);
-- 20P without counter (cont.)
component hex_display
port(bit_data: in std_logic_vector(15 downto 0);
LCD: out std_logic_vector( 6 downto 0);
int_clk: in std_logic; enable_0, enable_1,
enable_2, enable_3: out std_logic);
end component;
when 1 => Ld2 <= ‘1’; nextstate <= 2;
when 2|4|6|8|10 =>
if M = ‘1’ then Ad <= ‘1’; nextstate <= state + 1;
else Sh <= ‘1’; nextstate <= state + 2; end if;
when 3|5|7|9|11 =>
Sh <= ‘1’; nextstate <= state + 1;
when 12 =>
done <= ‘1’; nextstate <= 0;
if( Ld1 = ‘1’ ) then
acc(4 downto 0) <= InBus(4 downto 0); end if;
if( Ld2 = ‘1’ ) then mcand <= InBus( 7 downto 0 ); end if;
if( Ad = ‘1’ ) then acc( 13 downto 5 ) <= addout; end if;
341
Unit 20 Design Solutions
20.P
(cont.)
20P with counter
Accumulator[13:0]
Multiplier[4:0]
8Sh
Ld1
5
With Counter:
St'0
S1
S0
S3
S4
St Ld1
-Ld2
k Sh k'Sh
-done
k'M'
Sh
S2
kM'
Sh
done: out std_logic;
-- signals for hex display
int_clk: in std_logic;
hex_out: out std_logic_vector( 6 downto 0 );
e0, e1, e2, e3: out std_logic );
end lab20PwithCounter;
architecture behavioral of lab20PwithCounter is
signal state, nextstate: integer range 0 to 4;
signal mcand: std_logic_vector( 7 downto 0 );
-- 20P with counter (cont.)
begin
-- comment this line when simulating
hex: hex_display port map ( product, hex_out, int_clk,
e0, e1, e2, e3 );
product <= “000” & acc(12 downto 0);
-- we need 13 bits for 8 bit x 5 bit
addout <= (‘0’ & acc(12 downto 5 ) ) + mcand;
k <= ‘1’ when count = 4 else ‘0’;
process ( state, St, M, k ) begin
Ld1 <= ‘0’; Ld2 <= ‘0’; Sh <= ‘0’; Ad <= ‘0’; done <= ‘0’;
case state is
when 0 =>
if ( k = ‘1’ ) then nextstate <= 4;
else nextstate <= 2; end if;
when 4 => done <= ‘1’; nextstate <= 0;
end case;
end process;
process ( Clk, Rst ) begin
if ( Rst = ‘1’ ) then state <= 0; count <= “000”;
acc <= (others => ‘0’ ); mcand <= (others => ‘0’ );
342
Unit 20 Design Solutions
20.Q
20Q without counter
Clk
Accumulator[13:0]
Multiplier[7:0]
Ld1
8
8
Sh
No Counter:
S1
S0
S2S3
S4
St'0
St Ld1
-Ld2
M'
Sh
-done
20Q without counter
S16
S17 S18
M'
Sh
- Sh
- Sh
- Sh
-- 20Q without counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity lab20QwithoutCounter is
port (clk, st, Rst: in std_logic;
InBus: in std_logic_vector( 7 downto 0 );
-- 20Q without counter (cont.)
component hex_display
port( bit_data: in std_logic_vector(15 downto 0);
LCD: out std_logic_vector( 6 downto 0);
int_clk: in std_logic;
enable_0, enable_1, enable_2, enable_3: out std_logic );
end component;
begin
else nextstate <= 0; end if;
when 1 =>
ld2 <= ‘1’; nextstate <= 2;
when 2|4|6|8|10|12|14|16 =>
if ( m = ‘1’ ) then ad <= ‘1’; nextstate <= state + 1;
else sh <= ‘1’; nextstate <= state + 2; end if;
when 3|5|7|9|11|13|15|17 =>
sh <= ‘1’; nextstate <= state + 1;
when 18 =>
343
Unit 20 Design Solutions
20.Q
(cont.)
20Q with counter
Clk
Accumulator[13:0]
Multiplier[7:0]
8Sh
Counter
k
8
Ld1
"000"
With Counter:
S0
S4
St'
0
St
Ld1
-
done
20Q with counter
-- 20Q with counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
architecture behavioral of lab20QwithCounter is
signal state, nextstate: integer range 0 to 4;
signal mcand: std_logic_vector( 4 downto 0 );
signal count: std_logic_vector( 2 downto 0 );
-- 20Q with counter (cont.)
begin
-- comment this line when simulating
hex: hex_display port map ( product, hex_out, int_clk,
e0, e1, e2, e3 );
product <= “000” & acc(12 downto 0);
if ( st = ‘1’ ) then ld1 <= ‘1’; nextstate <= 1;
else nextstate <= 0; end if;
when 1 => ld2 <= ‘1’; nextstate <= 2;
when 2 =>
if ( m = ‘1’ ) then ad <= ‘1’; nextstate <= 3;
elsif ( k = ‘1’ ) then h <= ‘1’; nextstate <= 4;
process ( clk, Rst ) begin
if ( Rst = ‘1’ ) then state <= 0; count <= “000”;
acc <= (others => ‘0’); mcand <= (others => ‘0’);
elsif ( clk = ‘1’ and clk’event ) then
344
Unit 20 Design Solutions
20.R
Ld1
V
Dividend[10:0]
Sh
20R 6
Quotient [5:0]Remainder[4:0]
Su
No Counter:
S1
S0
S2
S8
S9
St'0
St Ld1
-Ld2
ovf'
- done
ovf
V
CSu C' -
-- 20R divider 6 / 4 bits to 6 bit quotient
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
architecture Behavioral_20R of divider_20R is
signal State, NextState: integer range 0 to 9;
signal C, Ld1, Ld2, Su, Sh, ovf: std_logic;
signal Subout: std_logic_vector(4 downto 0);
-- 20R divider 6 / 4 bits to 6 bit quotient (cont.)
process(St, State, C)
begin
Ld1 <= ‘0’; Ld2 <= ‘0’; Sh <= ‘0’; Su <= ‘0’; V <= ‘0’;
if C = ‘1’ then Su <= ‘1’; NextState <= state;
else Sh <= ‘1’; NextState <= state + 1; end if;
when 8 =>
NextState <= 9;
if C = ‘1’ then Su <= ‘1’;
else Su <= ‘0’; end if;
when 9 =>
if Ld1 = ‘1’ then
Dividend <= “00000”&Bus_in(5 downto 0); end if;
if Ld2 = ‘1’ then
Divisor <= Bus_in(3 downto 0); end if;
345
Unit 20 Design Solutions
20.S
Ld1
V
dividend[10:0]
Sh
20S 7
quotient [6:0]remainder[3:0]
Su
No Counter:
-- 20S divider 7 / 3 bits to 7-bit quotient
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity divider_20S is
Port( Bus_in: in std_logic_vector(6 downto 0);
Clk, St, Rst: in std_logic;
done, v: out std_logic;
-- 20S divider 7 / 3 bits to 7-bit quotient (cont.)
process(St, State, C)
begin
Ld1 <= ‘0’; Ld2 <= ‘0’; Sh <= ‘0’; Su <= ‘0’;
v <= ‘0’; done <= ‘0’;
if C = ‘1’ then Su <= ‘1’; NextState <= state;
else Sh <= ‘1’; NextState <= state + 1; end if;
when 9 =>
NextState <= 10;
if C = ‘1’ then Su <= ‘1’;
else Su <= ‘0’; end if;
when 10 =>
NextState <= 0; done <= ‘1’;
end case;
end process;
process(Clk, Rst)
S1
S0
S2
S9
St'0
St Ld1
-Ld2
ovf'
sh
- done
ovf
V
CSu
S10
C' -
346
Unit 20 Design Solutions
20.T
done
Clk
Z[3:0]
Ld3
4
4
4
"0000"
20T
No Counter:
S1
S2
St'0
St Ld1
-Ld2
S10
- Sh
-done
-Ld4
S12
S0
S11
-- 20T - multiplier 4 x 4 + 4 bits
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity mult4X4 is
architecture Behavioral of mult4X4 is
signal State, NextState: integer range 0 to 12;
signal ACC: std_logic_vector(8 downto 0);
alias M: std_logic is ACC(0);
-- 20T - multiplier 4 x 4 + 4 bits (cont.)
case State is
when 0 =>
if St = ‘1’ then Ld1 <= ‘1’; NextState <= 1;
else NextState <= 0; end if;
when 1 =>
else Sh<= ‘1’; NextState <= State + 2; end if;
when 4|6|8|10 =>
Sh <= ‘1’; NextState <= State + 1;
when 11 =>
Ld4 <= ‘1’; NextState <= 12;
when 12 =>
if Ld3 = ‘1’ then Z <= InBus(3 downto 0); end if;
if Ld4 = ‘1’ then
ACC (7 downto 0)<= adder2Output; end if;
if Ad = ‘1’ then ACC(8 downto 4) <= addout; end if;
if Sh = ‘1’ then
ACC <= ‘0’ & ACC(8 downto 1); end if;
State <= nextState;
end if;
347
Unit 20 Design Solutions
20.U
Z[4:0]
Ld3
5
20U
5
3
"000"
No Counter:
S1
S2
S3
S12
St'0
St Ld1
-Ld2
-Ld3
- Sh
M'
Sh
-Ld4
-done
S13
S14
S0
-- 20U Multiplier 3 * 5 + 5 Bits
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity mult3X5 is
Port(Clk, St ,Rst: in std_logic;
InBus: in std_logic_vector(4 downto 0);
done: out std_logic;
begin
Output <= ACC(7 downto 0);
adder2Output <= ACC(7 downto 0) + (“000” & Z);
addout <= (‘0’ & ACC(7 downto 5)) + Mcand;
process(St, State,M)
begin
-- 20U Multiplier 3 * 5 + 5 Bits (cont.)
case State is
when 0 =>
if St = ‘1’ then Ld1 <= ‘1’; NextState <= 1;
else NextState <= 0; end if;
when 1 =>
Ld2 <= ‘1’; NextState <= 2;
when 2 =>
Ld3 <= ‘1’; NextState <= 3;
when 3|5|7|9|11 =>
begin
if Rst = ‘1’ then State <= 0;
elsif Clk’event and Clk = ‘1’ then
if Ld1 = ‘1’ then
ACC(8 downto 5) <= “0000”;
348
Unit 20 Design Solutions
20.V
20V
Z[4:0]
Ld3
5
3
"000"
No Counter:
S1
St'0
St Ld1
-Ld2
- Sh
-done
-Ld4
S10
S9
S0
-- 20V - multiplier 5 x 3 + 5 bits
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
end mult5X3;
architecture Behavioral of mult5X3 is
signal State, NextState: integer range 0 to 10;
begin
Output <= ACC (7 downto 0);
adder2Output <= ACC(7 downto 0) + (“000” & Z);
addout <= (‘0’ & ACC(7 downto 3)) + Mcand;
process(St, State,M)
begin
-- 20V - multiplier 5 x 3 + 5 bits (cont.)
case State is
when 0 =>
if M = ‘1’ then Ad <= ‘1’; NextState <= State + 1;
else Sh<= ‘1’; NextState <= State + 2; end if;
when 4|6|8 =>
Sh <= ‘1’; NextState <= State + 1;
process(Clk,Rst)
begin
if rst = ‘1’ then state <= 0;
elsif Clk’event and Clk = ‘1’ then
if Ld1 = ‘1’ then
ACC(8 downto 3) <= “000000”;
349
Unit 20 Design Solutions
20.W
done
Clk
Z[5:0]
Ld3
6
20W
2
"00"
No Counter:
S1
S2
S3
S14
St'0
St Ld1 -Ld2
-Ld3
- Sh
M'
Sh
-done
-Ld4
S16
S0
S15
-- 20W - multiplier 2 x 6 + 6 bits
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity mult2X6 is
Port(Clk, St ,Rst: in std_logic;
InBus: in std_logic_vector(5 downto 0);
350
Unit 20 Design Solutions
-- 20W - multiplier 2 x 6 + 6 bits (cont.)
process(St, State,M)
begin
Ld1 <= ‘0’; Ld2 <= ‘0’; Ld3 <= ‘0’; Ld4 <= ‘0’;
Sh <= ‘0’; Ad <=’0’; done <= ‘0’;
case State is
when 0 =>
when 15 =>
Ld4 <= ‘1’; NextState <= 16;
when 16 =>
done <= ‘1’; NextState <= 0;
end case;
end process;
process(Clk,Rst)
begin
20.W
(cont.)

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