# Chapter 17 Shifting is like moving from AND gates involving

Type Homework Help
Pages 9
Words 220
Textbook Fundamentals of Logic Design 7th Edition
Authors Jr.Charles H. Roth, Larry L Kinney

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Unit 17 Solutions
See FLD p. 773 for solutions.
17.6 (a),
(b)
X1
4
X2
Z1
Z2
Unit 17 Problem Solutions
17.1 See FLD p. 770 for solution. 17.2 See FLD p. 770 for solution.
17.3 (a),
(b)
CO
Q(7)Q(6)Q(5)Q(4)
Q(3)Q(2)Q(1)Q(0)
CO ENT
CLRn
CLRn
CO1
17.7 (a) See FLD p. 774 for solution.
Q
Q(1)
Q
Q(2)
17.7 (b)
CE
Q
Q(1)
DCE
Q
D
Q(2)
17.8 See FLD p. 774 for solution.
Unit 17 Solutions
216
8
Q
En
Qint
17.12 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity myreg is
port(en, ld, clk : in std_logic;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity srff is
if (not s and r)='1' then qint <= '0';
elsif (s and not r)='1' then qint<='1';
elsif (s and r)='1' then qint<='X'; end if;
end if;
end process;
end Behavioral;
17.9 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- D-G Latch
end Behavioral;
-- D ip op using D-G latches
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
port (d, clk : in bit;
q : out bit);
17.10
Unit 17 Solutions
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encoder is
17.13 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comparator is
17.14
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity super is
begin
if clk' event and clk='1' then
case a is
when "111"=> qint <= d;
when "110"=> qint <= qint-1;
17.15 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcd_seven is
when "0010"=> seven <= "1011011";
when "0011"=> seven <= "1001111";
when "0100"=> seven <= "1100110";
when "0101"=> seven <= "1101101";
when "0110"=> seven <= "1111101";
17.16
Unit 17 Solutions
218
17.17 (a) library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mealy_XOR is
Port (CLK, clr, x : in std_logic;
z : out std_logic);
end Mealy_XOR;
0ns 40ns 80ns 120ns 160ns 200ns 240ns 280ns 320ns 360ns
CLK
clr
Signal
'0'
'1'
Current
17.17 (c)
17.17 (b)
17.17 (d)
0ns 40ns 80ns 120ns 160ns 200ns 240ns 280ns 320ns 360ns
CLK
clr
X
Signal
'0'
'1'
'1'
Current
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Moore_XOR is
Port (CLK, clr, X : in std_logic;
Z : out std_logic);
end Moore_XOR;
Unit 17 Solutions
219
0ns 40ns 80ns 120ns 160ns 200ns 240ns 280ns 320ns 360ns
CLK
Signal
'0'
Current
17.17 (e)
(cont.)
The Mealy model output is valid before the positive clock edge while the corresponding Moore model output
becomes valid after the clock edge. Also, the Mealy output is not valid after the clock edge until the input has
changed to its next value. The Meal model does not have an output corresponding to the Moore output prior to the
first clock edge.
)Z0 = Q0 Q1'Q3' or Q1'Q2'Q3'
Z1 = Q0 Q1
Z2 = Q0'Q1 Q2' or Q0'Q2'Q3'
17.18 (a)
D0 = Q1'Q2'
D1 = Q2'Q3'
D2 = Q0'Q3'
D3 = Q0'Q1'
17.18 (b)
CE0 = Q2', D0 = Q1' or CE0 = Q1', D0 = Q2'
CE1 = Q3', D1 = Q2' or CE1 = Q2', D1 = Q3'
17.18 (c)
17.18 (d) library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mod8_counter is
begin
Z0 <= '0'; Z1 <= '0'; Z2 <= '0'; Z3 <= '0';
Z4 <= '0'; Z5 <= '0'; Z6 <= '0'; Z7 <= '0';
case Q is
when "1000" =>
Z0 <= '1';
Q_plus <= "1100";
when "1100" =>
Z1 <= '1';
Q_plus <= "0100";
Q_plus <= "0001";
when "0001" =>
Z6 <= '1';
Q_plus <= "1001";
when "1001" =>
stt_trnstn: process(CLK,ClrN)
begin
if ClrN = '0' then
17.18 (d)
(cont.)
Unit 17 Solutions
220
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mod8_counter is
port (CLK, ClrN : in std_logic;
Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7 : out std_logic);
end mod8_counter;
architecture df1 of mod8_counter is
signal Q, D : std_logic_vector(0 to 3);
begin
cmb_lgc: process(Q)
begin
Z0 <= Q(0) and not Q(1) and not Q(3);
Z1 <= Q(0) and Q(1);
17.18 (e)
17.18 (e)
wave
form
0ns 40ns 80ns 120ns 160ns 200ns 240ns 280ns 320ns 360ns
CLK
ClrN
Z0
Z1
Signal
'1'
'1'
'0'
'1'
Current
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mod8_counter is
port (CLK, ClrN : in std_logic;
Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7 : out std_logic);
end mod8_counter;
architecture df2 of mod8_counter is
signal Q, CE, D : std_logic_vector(0 to 3);
begin
cmb_lgc: process(Q)
begin
Z0 <= Q(0) and not Q(1) and not Q(3);
Z1 <= Q(0) and Q(1);
17.18 (f)
Unit 17 Solutions
221
17.18 (f)
wave
form
0ns 40ns 80ns 120ns 160ns 200ns 240ns 280ns 320ns 360n
CLK
ClrN
Z0
Z1
Signal
'1'
'1'
'0'
'1'
Current
17.19 (d) library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mod8_counter2 is
port (CLK, ClrN : in std_logic;
Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7 : out std_logic);
end mod8_counter2;
when "1100" =>
Z1 <= '1';
Q_plus <= "1110";
when "1110" =>
Z2 <= '1';
Q_plus <= "0110";
when "0110" =>
Z3 <= '1';
Q_plus <= "0010";
when "0010" =>
when others =>
Q_plus <= "XXXX";
end case;
end process cmb_lgc;
17.19 (d)
(cont.)
)Z0 = Q0 Q1'Q3' or Q1'Q2'Q3'
Z1 = Q0 Q2'
Z2 = Q0 Q1 Q2 or Q0Q2Q3'
Z3 = Q0' Q1
Z4 = Q1'Q2 Q3' or Q0'Q1'Q3'
Z5 = Q0' Q3
17.19 (a)
CE0 = Q2', D0 = Q1' or CE0 = Q1', D0 = Q2'
CE1 = Q3', D1 = Q2' or CE1 = Q2', D1 = Q3'
CE2 = Q3', D2 = Q0' or CE2 = Q0', D2 = Q3'
CE3 = Q1', D3 = Q0' or CE3 = Q0', D3 = Q1'
17.19 (c)
Unit 17 Solutions
222
0ns 40ns 80ns 120ns 160ns 200ns 240ns 280ns 320ns 360ns
CLK
ClrN
Z0
Z1
Signal
'1'
'1'
'0'
'1'
Current
17.19 (e)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mod8_counter2 is
port (CLK, ClrN : in std_logic;
Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7 : out std_logic);
end mod8_counter2;
architecture df1 of mod8_counter2 is
signal Q, D : std_logic_vector(0 to 3);
begin
stt_trnstn: process(CLK,ClrN)
begin
if ClrN = '0' then
Q <= "1000";
elsif Rising_Edge (CLK) then
Q <= D;
17.19 (e) library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mod8_counter2 is
port (CLK, ClrN : in std_logic;
Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7 : out std_logic);
end mod8_counter2;
architecture df2 of mod8_counter2 is
signal Q, CE, D : std_logic_vector(0 to 3);
begin
stt_trnstn: process(CLK,ClrN)
begin
if ClrN = '0' then
Q <= "1000";
elsif Rising_Edge (CLK) then
if CE(0) = '1' then Q(0) <= D(0); end if;
17.19 (f)
Unit 17 Solutions
223
17.20(c)
library IEEE;
use IEEE.STD_LOGIC_1164 .ALL;
entity mag_comp_1bit is
port (a, b, gi, ei : in std_logic ;
go, eo : out std_logic );
end mag_comp_1bit ;
architecture Comp_Struc of mag_comp_4bit is
component mag_comp_1bit
port (a, b, gi, ei : in std_logic ;
go, eo : out std_logic );
end component ;
signal g, e : std_logic_vector (3 downto 0);
17.20(b)
library IEEE;
use IEEE.STD_LOGIC_1164 .ALL;
entity mag_comp_1bit is
port (a, b, gi, ei : in std_logic ;
go = gi OR (ei AND a AND b')
eo = ei AND ((a AND b) OR (a' AND b'))
17.20 (a)
0ns 40ns 80ns 120ns 160ns 200ns 240ns 280ns 320ns 360ns
CLK
ClrN
Z0
Z1
Signal
'1'
'1'
'0'
'1'
Current
17.19 (f)
a
b
17.20(c)
(cont.)
Unit 17 Solutions
224
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sm1 is
port (x, clk : in std_logic;
z : out std_logic);
end sm1;
17.22
17.21(c)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pr_sel_1bit is
port (a, si : in std_logic;
b, so : out std_logic);
end pr_sel_1bit;
architecture prdf of pr_sel_1bit is
begin
so <= si and not a;
b <= si and a;
architecture Pr_Struc of pr_sel_4bit is
component pr_sel_1bit
port (a, si : in std_logic;
b, so : out std_logic);
end component;
signal sel : std_logic_vector(3 downto 0);
begin
pr_sel_1bit_3 :pr_sel_1bit
port map (x(3), sel(3), y(3), sel(2));
pr_sel_1bit_2 :pr_sel_1bit
port map (x(2), sel(2), y(2), sel(1));
Time X isel Y osel sel
0 ns 1000 '1' 1000 '0' 1000
5 ns 0111 '1' 0100 '0' 1100
10 ns 0000 '1' 0000 '1' 1111
17.21 (d)
so = si AND a'
b = si AND a
17.21 (a) 17.21(b)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pr_sel_1bit is
so <= si and not a;
b <= si and a;
end prdf;
a
Unit 17 Solutions
225
--The state assignment is as follows (q0q1q2q3)-
--S0 - 1000; S1 - 0100; S2 - 0010; S3 - 0001
--VHDL code using equations derived by inspection from state graph
entity sm1 is
port (x, clk : in bit;
z : out bit);
end sm1;
17.23
S0S1
XZ
X'
0
X0
X'0
X0
X'
Z
17.24 There are three problems with this code.
1) The sensitivity list for the process contains the signal select. It should be sel. (Select is a VHDL reserved
word).
17.27
State
Next State
X1X2 = 00 01 10 11
Z
S0 S0 S1 S2 S00
State
Next State
X = 0 X = 1
Output
X = 0 X = 1
S0 S0 S110 00
17.25
State
Next State
X = 0 X = 1
Output
S0 S0 S11
17.26
Unit 17 Solutions
226
Ck
D Q
Q'
clr
y0
17.29 df1, df2, and df3 are the same. They have two ip-ops, y0 and y1; y1 has input xin and y0 has input the
complement of y0. The output z is y0 AND (xin XOR y1 or equivalent AND-OR logic.
17.28 (a) Present
State
Next State
xin = 0 xin = 1
zout
S1 S2 S10 0
S2 S2 S30
S3 S4 S61
17.28 (b)
0ns 40ns 80ns 120ns 160ns 200ns 240ns 280ns 320ns 360ns
clk
rst
xin
Signal
'0'
'0'
'1'
Current
17.28 (c) Present
State
Next State
xin = 0 xin = 1
zout
S1 S2 S60
S2 S2 S30
S3 S4 S61
Unit 17 Solutions
227
Ck
D Q
Q'
clr
y0
df4 is the same except that z is "registered" in a ip-op.
17.29 (b) The output for df4 only changes on positive clock edges and is delayed with respect to the output for df1, df2 and df3.
See the simulation waveforms below..
0ns 40ns 80ns 120ns 160ns 200ns 240ns 280ns 320ns 360ns
clk
rst
Signal
'0'
'0'
Current
0ns 40ns 80ns 120ns 160ns 200ns 240ns 280ns 320ns 360ns
clk
rst
Signal
'0'
'0'
Current
Simulation for df4.
Simulation for df1, df2 and df3.
17.29
(cont.)
Unit 17 Solutions
8
Z
17.30 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
port (X : in std_logic_vector(7 downto 0);
Store, Set, Clk : in std_logic;
Z : out std_logic_vector(7 downto 0));
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Seq_143 is
port (Clk, X : in std_logic;
Z : out std_logic);
when 0 => Z <= '0';
if X = '0' then NextState <= 0;
else NextState <= 1; end if;
when 1 => Z <= '0';
if X = '0' then NextState <= 2;
else NextState <= 1; end if;
when 2 => Z <= '0';
if X = '0' then NextState <= 0;
17.31

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