Unit 17 Solutions
222
0ns 40ns 80ns 120ns 160ns 200ns 240ns 280ns 320ns 360ns
CLK
ClrN
Z0
Z1
Signal
‘1’
‘1’
‘0’
‘1’
Current
17.19 (e)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mod8_counter2 is
port (CLK, ClrN : in std_logic;
Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7 : out std_logic);
end mod8_counter2;
architecture df1 of mod8_counter2 is
signal Q, D : std_logic_vector(0 to 3);
begin
stt_trnstn: process(CLK,ClrN)
begin
if ClrN = ‘0’ then
Q <= “1000”;
elsif Rising_Edge (CLK) then
Q <= D;
17.19 (e) library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mod8_counter2 is
port (CLK, ClrN : in std_logic;
Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7 : out std_logic);
end mod8_counter2;
architecture df2 of mod8_counter2 is
signal Q, CE, D : std_logic_vector(0 to 3);
begin
stt_trnstn: process(CLK,ClrN)
begin
if ClrN = ‘0’ then
Q <= “1000”;
elsif Rising_Edge (CLK) then
if CE(0) = ‘1’ then Q(0) <= D(0); end if;
17.19 (f)