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113
Unit 10 Solutions
Unit 10 Problem Solutions
10.1 See FLD p. 747 for solution. 10.2 See FLD p. 747 for solution.
10.3
See FLD p. 748 for solution
10.4 See FLD p. 748 for solution.
10.5 See FLD p. 748 for solution.
Notes: The function vec2int is found in bit_pack, which is in the library bitlib, so the following declarations are
10.6 See FLD p. 748 for solution. 10.7 See FLD p. 749 for solution.
Notes: In line 8, "00"&a converts a to a 18-bit
std_logic_vector. The overloaded “+” operators
10.9 See FLD p. 749 for solution.
10.10 The circuit represented by the given code is:
P
Q R
L
M
AN <= not A after 5 ns;
C <= AN nand B after 10ns;
H <= not A nand B nor not D nand E;
10.11 (a) 10.11(b)
114
Unit 10 Solutions
F <= not A after 15ns when C&D = "00"
entity mynand is
port(X, Y: in bit; Z: out bit);
end mynand;
10.18 (a)
port(A, B, C, D: in bit; F: out bit);
end main;
architecture eqn of main is
component mynand is
10.17 (a) with C&D select
10.17 (b)
library bitlib;
use bitlib.bit_pack.all;
entity myrom is
port (A, B, C, D: in bit; W, X, Y: out bit);
end myrom;
10.15 databus <= membus when mRead = '1'
else "ZZZZZZZZ";
databus <= probus when mWrite = '1'
else "ZZZZZZZZ";
10.16 (a)
10.12
10.14 (a) The expression can be rewritten as:
L = X (Since 1 and 0 in the resolution function
yields X)
10.13
LHS: not("101" & "011") = "010100"
10.14 (b)
115
Unit 10 Solutions
0ns 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns
a
b
Si gnal
' 1'
' 0'
Cur r ent
10.19(b)
10.19(a) library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hazard_circuit is
port (a, b, c : in std_logic;
10.19(c) change the assignment statement for d to
d <= not b after 5 ns;
change the assignment statement for f to
f <= transport e or g after 10 ns;
10.19(e)
0ns 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns
a
b
c
Si gnal
' 1'
' 0'
' 1'
Cur r ent
10.19(d)
0ns 10ns 20ns 30ns 40ns 50ns 60ns 70ns
a
b
c
Si gnal
' 1'
' 0'
' 1'
Cur r ent
10.19 (f)
116
Unit 10 Solutions
10.20(a) library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dynhaz_circuit is
port (a, b, c, d : in std_logic;
f : out std_logic);
end dynhaz_circuit;
10.20(c) change the assignment statement for e to
e <= not b after 5 ns;
change the assignment statements for j and f to
j <= transport g orh after 10 ns;
f <= transport i or j after 10 ns;
10.20(e)
0ns 15ns 30ns 45ns 60ns 75ns 90ns 105ns
a
b
c
Signal
'1'
'0'
'1'
Current
10.20(b)
0ns 15ns 30ns 45ns 60ns 75ns 90ns 105ns
a
b
c
d
Signal
'1'
'0'
'1'
'0'
Current
10.20(d)
117
Unit 10 Solutions
10.21(a)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
0ns 15ns 30ns 45ns 60ns 75ns 90ns 105ns
a
b
c
d
Signal
'1'
'0'
'1'
'0'
Current
10.20(f)
architecture behavioral1 of bcd_to_2421 is
begin
10.21(c)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bcd_to_2421 is
10.21(b)
& (d)
Time x y
0 ns 0100 0100
architecture behavioral2 of bcd_to_2421 is
begin
with x select
"1100" when "0110",
"1101" when "0111",
"1110" when "1000",
118
Unit 10 Solutions
10.22(a)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity c8421_to_excess3 is
port (x : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0));
end c8421_to_excess3;
architecture behavioral1 of c8421_to_excess3 is
begin
y <= "0011" when x = "0000"
else "0100" when x = "0111"
10.22(c)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity c8421_to_excess3 is
port (x : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0));
end c8421_to_excess3;
architecture behavioral2 of c8421_to_excess3 is
begin
with x select
10.22(b)
Time x y
0 ns 0100 0111
5 ns 0101 0110
Time x y
0 ns 0011 XXXX
5 ns 0100 0111
10.22(d)
