# Chapter 20 Next state Integer Range Replace Lines With When

Type Homework Help
Pages 6
Words 37
Textbook Fundamentals of Logic Design 7th Edition
Authors Jr.Charles H. Roth, Larry L Kinney

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257
Unit 20 Solutions
Unit 20 Problem Solutions
20.1 See FLD p. 781 for solution. 20.2 See FLD p. 781-782 for solution.
20.3 Replace line 12 with:
signal State, Nextstate: integer range 0 to 5;
Replace lines 27 - 33 with:
when 1 | 2 | 3 | 4 =>
See FLD p. 782-783 for solution.
20.4
20.5
Replace line 14 with:
signal Counter: integer range 0 to 4;
signal State, NextState: integer range 0 to 3;
K<='1' when Counter=3 else '0';
20.7
Clk
Rb
Reset
20.8
20.8
(cont.)
Entity and architecture for DiceGame goes here.
entity GameTest is
end GameTest;
architecture dicetest of GameTest is
component DiceGame
port (CLK, Rb, Reset : in bit;
Contintued next column
process
begin
for i in 0 to 11 loop
Rb <= '1'; -- push roll button
wait until roll = '1';
wait until clk'event and clk = '1';
Rb <= '0'; -- release roll button
wait; -- test completed, do not execute process
again
end process;
end dicetest;
258
Unit 20 Solutions
Replace lines 6 - 11 with:
Port (Dividend_in: in std_logic_vector(4 downto 0);
Divisor: in std_logic_vector(4 downto 0);
St, Clk: in std_logic;
Quotient: out std_logic_vector(4 downto 0);
Remainder: out std_logic_vector(4 downto 0);
Replace lines 14 - 17 with:
signal State, NextState: integer range 0 to 6;
Replace line 25 with:
Load <= '0'; Sh <= '0'; Su <= '0';
Replace lines 28 - 33 with:
if (St = '1') then
if (V='0') then Load <='1'; NextState <= 1;
else Nextstate <= 0; end if;
else Nextstate <= 0; end if;
20.9
259
Unit 20 Solutions
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mult20_10 is
architecture Behavioral of mult20_10 is
signal State, NextState: integer range 0 to 4;
signal A, B: std_logic_vector (3 downto 0); -- Multiplicand & Multiplier
signall PU, PL: std_logic_vector (3 downto 0); -- Product registers
signal muxout, andarray: std_logic_vector (3 downto 0);
begin
CP <= '0'; LA <= '0'; DB <= '0'; MS <= '0'; CC <= '0';
EA <= '0'; LPU <= '0'; LPL <= '0'; D <= '0'; -- control signals are '0' by default
case State is
when 0 =>
CP <= '1'; LA <= '1'; CC <= '1';
if S = '1' then NextState <= 1; else NextState <= 0; end if;
process (CLK)
begin
if CLK'event and CLK = '1' then -- update registers on rising edge of clk
if LA = '1' then B <= Mplier; A <= Mcand; end if; -- load multiplier & multiplicand
if CP = '1' then PU <= "0000"; PL <= "0000"; end if; -- clear product registers
20.10 (a)
Unit 20 Solutions
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test20_10 is
end test20_10;
constant N: integer := 4;
type arr is array(1 to N) of std_logic_vector(3 downto 0);
constant Mcandarr: arr := ("1011", "1011", "1111", "0000");
constant Mplierarr: arr := ("0101", "0000", "1111", "1111");
signal CLK: std_logic :='0';
signal S, D: std_logic;
S <= '0';
wait until D = '1' ;
wait until CLK = '1' and CLK'event;
end loop;
end process;
end test1;
20.10 (b)
261
Unit 20 Solutions
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mult20_11 is
Port (CLK, S: in std_logic;
architecture Behavioral of mult20_11 is
signal State, NextState: integer range 0 to 4;
signal B: std_logic_vector (3 downto 0); -- Multiplier counter
signal A: std_logic_vector (3 downto 0); -- Multiplicand register
signal PU: std_logic_vector (3 downto 0); -- Upper half of product register
begin
BZ <= '1' when B = "0000" else '0';
muxout <= PU when MS = '1' else PL;
andarray <= A when EA = '1' and IA = '0' else
not A when EA = '1' and IA = '1' else
"1111" when EA = '0' and IA = '1' else "0000";
addout <= ('0' & muxout) + ('0' & andarray) + ("0000" & C); -- adder output is 5 bits
Product <= PU & PL; -- including carry
process (S, State, BZ)
begin
CP <= '0'; LA <= '0'; DB <= '0'; IB <= '0'; MS <= '0'; CC <= '0'; -- control signals are '0'
SC <= '0'; EA <= '0'; IA <= '0'; LPU <= '0'; LPL <= '0'; D <= '0'; -- by default
20.11 (a)
262
Unit 20 Solutions
process (CLK)
begin
if CLK'event and CLK = '1' then -- update registers on rising edge of clk
if LA = '1' then B <= Mplier;
A <= Mcand; end if; -- load multiplier & multiplicand
20.11 (a)
(cont.)
--Same as 20-10(b) except
constant N: integer := 6;
type arr is array(1 to N) of std_logic_vector(3 downto 0);
20.11 (b)

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