Unit 8 Design Solutions
Problems 8.A through 8.S are combinational logic design problems using NAND and NOR gates.
Problems 8.A through 8.R are of approximately equal difficulty so that different students in the
class can be assigned different problems. We ask our students to use the following procedure:
(1) Derive a truth table for the assigned problem.
(2) Use Karnaugh maps to derive logic equations in sum-of-products or product-of-sums form
depending on whether NAND gates or NOR gates are required.
(3) Enter the truth table into LogicAid, derive the logic equations, and check the answers
In Unit 10, we ask our students to implement the same design problem using VHDL, synthesize it
and download it to a CPLD or FPGA on a hardware board that has switches, LEDs, and 7-segment
indicators.
For each design problem, the solutions that follow show a SimUaid circuit that meets the problem
8.A X1 = B’D’ + B D + A + C D = B’D’ + BC’D + A + CD (used in circuit)
X1 = B’D’ + B D + A + B’C
X2 = B’ + C’D’ + C D
X3 = C’ + D + B
X4 = B’D’ + B’C + B C’D + C D’
X5 = B’D’ + C D’
0000 1 1 1 1 1 1 0
0001 0 1 1 0 0 0 0
0010 1 1 0 1 1 0 1
0011 1 1 1 1 0 0 1
ABCD X
1
X
2
X
3
X
4
X
5
X
6
X
7
III. SOLUTIONS TO DESIGN, SIMULATION,
AND LAB EXERCISES
Solutions to Unit 8 Design Problems