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Timing refers to the way in which events are coordinated on the bus.
A microcomputer architecture and organization relationship is not very close.
Machine parallelism exists when instructions in a sequence are independent and thus
can be executed in parallel by overlapping.
An interrupt is a hardware-generated signal to the processor.
Nonvolatile means that power must be continuously supplied to the memory to preserve
the bit values.
A straight comparison of clock speeds on different processors tells the whole story
about performance.
Register addressing is similar to direct addressing with the only difference being that
the address field refers to a register rather than a main memory address.
The "read word from memory" and "increment PC" actions cannot be used
simultaneously because they will interfere with each other.
The reorder buffer is temporary storage for results completed out of order that are then
committed to the register file in program order.
The L1 cache is slower than the L3 cache.
There are typically hundreds of sectors per track and they may be either fixed or
variable lengths.
With a batch operating system the user does not have direct access to the processor.
The advantage of RAM is that the data or program is permanently in main memory and
need never be loaded from a secondary storage device.
Register indirect addressing uses the same number of memory references as indirect
addressing.
ARM architecture has yet to implement superscalar techniques in the instruction
pipeline.
The increasingly difficult engineering challenge related to processor logic is one of the
reasons that an increasing fraction of the processor chip is devote to the simpler
memory logic.
To achieve greatest performance the memory must be able to keep up with the
processor.
ARM provides a versatile virtual memory system architecture that can be tailored to the
needs of the embedded system designer.
Interfaces between the computer and peripherals is an example of an organizational
attribute.
One boundary where the computer designer and the computer programmer can view the
same machine is the machine instruction set.
Uniprogramming is the central theme of modern operating systems.
Even if an individual application does not scale to take advantage of a large number of
threads, it is still possible to gain from multicore architecture by running multiple
instances of the application in parallel.
Cache is not a form of internal memory.
A cycle is made up of a sequence of micro-operations.
Because data are striped in very small strips, RAID 3 cannot achieve very high data
transfer rates.
One of the major problems in designing an instruction pipeline is assuring a steady flow
of instructions to the initial stages of the pipeline.
The demand on power requirements has not grown as chip density and clock frequency
have risen.
In effect, the Intel Core architecture implements a CISC instruction set architecture on a
RISC microarchitecture.
A microprogram consists of a sequence of instructions in a microprogramming
language.
An advantage of biased representation is that nonnegative floating-point numbers can
be treated as integers for comparison purposes.
The disadvantage of using CAV is that individual blocks of data can only be directly
addressed by track and sector.
Typically an instruction set will include both preindexing and postindexing.
The method of calculating the EA is the same for both base-register addressing and
indexing.
Historically the distinction between architecture and organization has not been an
important one.
Computer organization refers to attributes of a system visible to the programmer.
Overflow can only occur if there is a carry.
Operations performed by a processor, such as fetching an instruction, decoding the
instruction, performing an arithmetic operation, and so on, are governed by a system
clock.
In the scalar organization there are multiple functional units, each of which is
implemented as a pipeline and provides a degree of parallelism by virtue of its
pipelined structure.
The big.Little architecture uses a combination of ARM Cortex-A7 and Cortex A-15
cores.
For base 2 representation, a normal number is one in which the most significant bit of
the significand is zero.
Putting rendering on one processor, AI on another, and physics on another is an
example of _________ threading.
A. coarse-grained
B. multi-instance
C. fine-grained
D. hybrid
The advantages of _________ addressing are that only a small address field is needed
in the instruction and no time-consuming memory references are required.
A. direct
B. indirect
C. register
D. displacement
A DDR3 module transfers data at a clock rate of __________ Mbps.
A. 600 to 1200
B. 800 to 2133
C. 1000 to 2000
D. 1500 to 3000
Numbers in the binary system are represented to the _________.
A. base 0
B. base 1
C. base 2
D. base 10
If a programmer wished to program directly in machine language it would be necessary
to enter the program as ________ data.
_________ is determined by the number of instructions that can be fetched and
executed at the same time and by the speed and sophistication of the mechanisms that
the processor uses to find independent instructions.
A. Machine parallelism
B. Instruction-level parallelism
C. Output dependency
D. Procedural dependency
Machine cycles are defined to be equivalent to ________ accesses.
A. flag
B. bus
C. clock
D. path
A(n) _________ expresses operations in a concise algebraic form using variables.
A. opcode
B. high-level language
C. machine language
D. register
________ is when the DMA module must force the processor to suspend operation
temporarily.
A. Interrupt
B. Thunderbolt
C. Cycle stealing
D. Lock down
The von Neumann architecture is based on which concept?
A. data and instructions are stored in a single read-write memory
B. the contents of this memory are addressable by location
C. execution occurs in a sequential fashion
D. all of the above
Which of the following is a LSI-11 microinstruction?
A. add word
B. test word
C. Jump
D. all of the above
A computer must be able to process, store, move, and control data.
SPARC refers to an architecture defined by ________.
A. Microsoft
B. Apple
C. Sun Microsystems
D. IBM
Which stage is required for load and store operations?
A. I
B. E
C. D
D. all of the above
A(n) _________ is generated by a failure such as power failure or memory parity error.
A. I/O interrupt
B. hardware failure interrupt
C. timer interrupt
D. program interrupt
An I/O module that is quite primitive and requires detailed control is usually referred to
as an _________.
A. I/O command
B. I/O controller
C. I/O channel
D. I/O processor
The _________ defines the system call interface to the operating system and the
hardware resources and services available in a system through the user instruction set
architecture.
A. HLL
B. API
C. ABI
D. ISA
The ________ pulse signals the start of each machine cycle from the control unit and
alerts external circuits.
A. AC
B. INSTR
C. ALE
D. OUT
Indexing performed after the indirection is __________.
A. relative addressing
B. autoindexing
C. postindexing
D. preindexing
Vector and array processors fall into the ________ category of computer systems.
A. SIMD
B. SISD
C. MISD
D. MIMD
__________ are a set of storage locations.
A. Processors
B. PSWs
C. Registers
D. Control units
All instructions in the ARM architecture are __________ bits long and follow a regular
format.
A. 8
B. 16
C. 32
D. 64
________ is when the processor spends most of its time swapping pages rather than
executing instructions.
A. Swapping
B. Thrashing
C. Paging
D. Multitasking
A taxonomy first introduced by _______ is still the most common way of categorizing
systems with parallel processing capability.
A. Randolph
B. Flynn
C. von Neuman
D. Desai
In embedded systems the GPU is composed of only a single-digit number of cores, and
are typically combined with a number of conventional cores, referred to as _________.
A. arithmetic logic units
B. control units
C. central processing units
D. graphic processing units
Computer technology is changing at a __________ pace.
A. slow
B. slow to medium
C. rapid
D. non-existent
The operation _________ yields true if either or both of its operands are true.
A. NOT
B. AND
C. NAND
D. OR
Which of the following memory types are nonvolatile?
A. erasable PROM
B. programmable ROM
C. flash memory
D. all of the above
A sequence of codes or instructions is called __________.
A. software
B. memory
C. an interconnect
D. a register
The operation of the digital computer is based on the storage and processing of binary
data.
The control unit controls the internal flow of data.
The term microprogram was first coined by __________ in the early 1950s.
A. M.V. Wilkes
B. D. Siewiorek
C. M. Sebern
D. S. Tucker
_________ formats extend a supported basic format by providing additional bits in the
exponent and in the significand.
A. Arithmetic
B. Basic
C. Extended precision
D. Interchange
The __________ are used to designate the source or destination of the data on the data
bus.
A. system lines
B. data lines
C. control lines
D. address lines
CUDA was created by __________ .
A. Amdahl
B. NVIDIA
C. the U.S. Government
D. Herbert Moore
In a _________ disk there is one read-write head per track and all of the heads are
mounted on a rigid arm that extends across all tracks.
_________ occurs when an arithmetic operation results in an absolute value greater
than can be expressed with an exponent of 128.
_________ registers enable the machine or assembly language programmer to minimize
main memory references by optimizing use of registers.
The unit of transfer at the link layer is a phit and the unit transfer at the physical layer is
a flit.
The simplest form of addressing is __________ addressing.
As chip tristor density has increased, the percentage of chip area devoted to memory
has decreased.
__________ applications are characterized by having a small number of highly
threaded processes.
In the _________ system, 10 different digits are used to represent numbers with a base
of 10.
From the point of view of an A15 core, an interrupt can be active, inactive, or
__________ .
Source and result operands can be in one of four areas: main or virtual memory,
immediate, I/O device, and _________.
With _________ transmission signals are transmitted as a current that travels down one
conductor and returns on the other.
__________ computing deals with super computers and their software.
RAID levels 4 through 6 make use of an __________ access technique that allows
separate I/O requests to be satisfied in parallel.
__________ is a process where new inputs are accepted at one end before previously
accepted inputs appear as outputs at the other end.
In a ________ microinstruction a code is used for each action to be performed and the
decoder translates this code into individual control signals.
A typical DRAM pin configuration will include the __________ pin if necessary in
order to have an even number of pins.
