Problem Solutions – Chapter 5
1
CHAPTER 5
© 2016 Pearson Education, Inc.
5-1.*
a)
F (A B)CD
5-2.
a) 3-input NAND gate
+V
A
B
+V
+V
a) 3–input NAND gate b) 4–input NOR gate
b) 4-input NOR gate +V
+V
A
+V
+V
a) 3–input NAND gate b) 4–input NOR gate
5-3.
Problem Solutions – Chapter 5
2
5-4.
a)
b) 4K×32/(256×8) = 64 ROM chips
5-5.* (Errata: Change “32 X 8” to “64 X 8” ROM)
IN
OUT
IN
OUT
IN
OUT
IN
OUT
000000
0000 0000
010000
0001 0110
100000
0011 0010
110000
0100 1000
000001
0000 0001
010001
0001 0111
100001
0011 0011
110001
0100 1001
000010
0000 0010
010010
0001 1000
100010
0011 0100
110010
0101 0000
000011
0000 0011
010011
0001 1001
100011
0011 0101
110011
0101 0001
5-6.
a) 16 + 16 + 1 = 33 address bits and 16 + 1 = 17 output bits, 8G × 17
A
8
A
9
1
2
3
256 x 8 ROM
8
256 x 8 ROM
Address
8
256 x 8 ROM
Address
8
256 x 8 ROM
Address
8
256 x 8 ROM
Address
8
256 x 8 ROM
8
8
8
8
8
8
8
A
0
A
DECODER
0
1
256 x 8 ROM
Address
EN
8
8
A
(7:0)
8
8
256 x 8 ROM
Address
EN
000100
0000 0100
010100
0010 0000
100100
0011 0110
110100
0101 0010
000101
0000 0101
010101
0010 0001
100101
0011 0111
110101
000110
0000 0110
010110
0010 0010
100110
0011 1000
110110
0101 0100
000111
0000 0111
010111
0010 0011
100111
0011 1001
110111
0101 0101
001000
0000 1000
011000
0010 0100
101000
0100 0000
111000
0101 0110
001001
0000 1001
011001
0010 0101
101001
111001
0101 0111
001010
0001 0000
011010
0010 0110
101010
0100 0010
111010
0101 1000
001011
0001 0001
011011
0010 0111
101011
0100 0011
111011
0101 1001
001100
0001 0010
011100
0010 1000
101100
0100 0100
111100
0110 0000
001101
0001 0011
011101
101101
0100 0101
111101
0110 0001
001110
0001 0100
011110
0011 0000
101110
0100 0110
111110
0110 0010
001111
0001 0101
011111
0011 0001
101111
0100 0111
111111
0110 0011
Problem Solutions – Chapter 5
3
5-7.
Input
Output
X
Y
Z
A
B
C
D
0
0
0
1
0
0
0
5-8.
Y
Y
Y
Y
A B C D
11
1
11
1
1
1
5-9.
Find the truth table and K-maps:
X
Y
Z
A
B
C
D
E
F
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
0
1
1
0
0
0
1
0
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
1
0
0
1
0
0
1
1
1
1
1
0
0
0
1
X
Y
Z
X
Y
Z
X
Y
Z
11
1
1 1
1
ABC
Find the truth table and K-maps:
X Y Z A B C D E F
000000000
001000001
1
X
Y
X
Y
X
Y
11
1
1 1
1
ABC
Find the truth table and K-maps:
X Y Z A B C D E F
0 0 0 0 0 0 0 0 0
1
0
0
1
1
0
0
1
1
0
0
0
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
1
0
0
1
Problem Solutions – Chapter 5
4
5-10.
The values given in the four K-maps come from Table 4-4 on page 224.
C
C
C
C
WX Y Z
The v alues giv en in the f our K-maps come f rom Table 3-1 on page 99.
10 0 110 0 01 100 00
1 1
5-11.*
Assume 3-input OR gates.
Assume 3-input OR gates.
C
C
C
C
W
10 0 110 0 01 100 00
1 1
5-12.
Figure 5-10 uses 3-input OR gates.
Y
Y
Y
Y
ABCD
Figure 6-23 uses 3-input OR gates.
Problem Solutions – Chapter 5
5
5-13.
Figure 5-10 uses 3-input OR gates.
Straightforward implementation of F requires five prime implicants and of G requires four prime implicants, but only 3
inputs are available on the PAL OR gates. So sum-of-products that can be factored from F and G or both and
5-14.
a)
( , , ) ( ) ( ) F A B C C AB B C AB A
5-15.
a)
A
B
D
A
B
D
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
C
F
1
G
Problem Solutions – Chapter 5
6
b) Using Shannon’s expansion theorem,
( , , , ) ( ( ) (1)) ( ( ) ( )) F A B C D D C A B C D C A C A
. Then using the 4-
5-16.
Assuming that the upper input of each mux is selected with a 0:
5-17.
5-18.
The state machine is a Moore machine since the output Z depends only the current state. Using a state assignment of 0