Problem Solutions – Chapter 3
1
CHAPTER 3
© 2016 Pearson Education, Inc.
3-1.
Place a 1 in each K-map cell where 2 or more inputs are equal to 1.
3-2.*
C
3-3.
Assuming inputs G3, G2, G1, G0 and outputs B3, B2, B1, B0, with G3 and B3 being the most significant bits, and treating the invalid
input combinations as don’t cares:
3-4. a) For the 3 x 3 pattern, there are exactly three row, three column and two diagonal combinations that represent a win for the X
3-5. a) For the 4 x 4 pattern, there are exactly four row, four column and two diagonal combinations that represent a win for the X
Problem Solutions – Chapter 3
2
3-6.
a) Detecting a change in one-out-of-
three inputs can be done using a parity
X1
X2
X3
Z
3-7.+
ABCD
GNS
YNS
RNS
GEW
YEW
REW
0000
1
0
0
0
0
1
0001
1
0
0
0
0
1
0011
1
0
0
0
0
1
0010
1
0
0
0
0
1
0110
1
0
0
0
0
1
0111
1
0
0
0
0
1
0101
0
1
0
0
0
1
0100
0
0
1
0
0
1
1100
0
0
1
1
0
0
1101
0
0
1
1
0
0
1111
0
0
1
1
0
0
1110
0
0
1
1
0
0
1010
0
0
1
1
0
0
1011
0
0
1
1
0
0
1001
0
0
1
0
1
0
1000
0
0
1
0
0
1
B
A
GNS
B
3-8.
A
B
C
S5
S4
S3
S2
S1
S0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
0
1
1
0
0
0
1
0
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
1
0
0
1
0
0
1
1
1
1
1
0
0
0
1
S0 C
S1 0
0
0
1
1
0
1
0
1
1
1
1
1
Problem Solutions – Chapter 3
3
3-9.+
A
B
C
D
S2
S1
S0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
S0 BCD BCD AB ACD ABCD
3-10.
A
B
C
D
W
X
Y
Z
0
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
0
0
0
0
1
1
0
1
0
0
1
0
1
1
1
1
0
1
0
1
0
0
0
1
0
1
1
1
0
0
1
1
1
0
0
W AC BD BD
X BCD BC+BD
0
0
1
0
0
0
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
0
1
0
1
0
1
0
0
1
1
0
0
1
0
0
1
1
1
0
1
1
1
0
0
0
0
1
1
1
0
0
1
0
1
1
1
0
1
0
0
1
1
1
0
1
1
0
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
0
1
1
1
1
1
0
0
Problem Solutions – Chapter 3
3-11.
a)
PS
LS
RS
RR
PL
LL
RL
0
0
0
0
0
0
0
0
0
0
1
0
0
0
PL PS
LL PS LS RS PS LS RR
RL PS LS RS PS RS RR
3-12.
b)
a = AC + ABD + ABD + ABC
b = AB + BC + ACD + ACD
C
C
C
C
1
1
1
1
1
1
1 1
11
11
1 1
11
1
1
1
1
1
1
1
1
a)
4
0
0
1
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0
0
1
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
0
1
1
1
0
1
0
1
0
0
0
1
0
0
1
0
0
1
1
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
0
1
1
0
0
1
0
0
1
1
0
1
1
0
0
1
1
1
0
1
0
0
1
1
1
1
1
0
0
Problem Solutions – Chapter 3
5
3-13.
X
Y
W=XZ + YZ
Hierarchy
X
Y
Z
W
3-14.
Hierarchy
X
Y
H
G
G = A(BC +BD)+ A(BC+BD)
3-15.+
Problem Solutions – Chapter 3
6
3-16.
A
B
A
B
C
A
B
C
3-17.
A
B
C
D
E
G
A
B
C
D
Problem Solutions – Chapter 3
7
1) Original circuit using AND, OR, Inverter
Problem Solutions – Chapter 3
3-19.
For original circuit, see 3-18 part (a) above.
a) Mapped to Inverter, 2NOR, 3NOR, and 4NOR
3-20.
X
1
T XY
3-21.
G1
the outputs Y0 through Y7 are all 1’s. Oth
Y = ABCE
0
Except for G1 = 1 and G2A and G2B =
0, the outputs Y0 through Y7 are all 1’s.
8
Problem Solutions – Chapter 3
3-22.
3-23.
a)
b) Treating the input values 1010-1111 as don’t cares changes the behavior for those values:
3-24. *
F7
F6
VDD
a) b)
G7
G6
A
A
Problem Solutions – Chapter 3
3-25.
F7
VDD
a) b)
G7
VDD
3
3-26.
a) b)
11
5
0
1
3-27.
0 1 2 3 4 5
(
A S S S S S S M
S5
S4
V
C
3-28.
A0
D0
D8
DECODER
0
A0
DECODER
)
10
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they
currently
exist. No portion of this material may be reproduced, in anhout permission in writing from the
publisher.
Problem Solutions – Chapter 3
11
3-29.
A0
A1
DECODER
A0
A1
DECODER
0
1
2
3
En
D0
D1
D2
D3
3-30.*
Problem Solutions – Chapter 3
3-31. (Errata: Replace “4” with “3” in “4–to-6-line decoder”)
DECODER
3-32.
a) The Truth Table:
Note: a = g, b = f, and c = e.
a) The Truth Table:
X2X1X0a b c d e f g
0 0 0 d d d d d d d
0 0 1 0 0 0 1 0 0 0
DECODER
Note: a = g, b = f , and c = e.
12
Problem Solutions – Chapter 3
13
3-33.
A1
D0
D1
A0
3-34.
C2
C1
K–Map for GE5: BCD = (C3,C2, C1, C0)
1 1 1
d d dd
Problem Solutions – Chapter 3
3-35.*
D3
D2
D1
D0
A1
A0
V
0
0
0
0
X
X
0
D1
D0
A1
X
D0
D1
A1
3-36.
Decimal Inputs
Binary Outputs
9
8
7
6
5
4
3
2
1
0
A3
A2
A1
A0
V
0
0
0
0
0
0
0
0
0
0
X
X
X
X
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
X
0
0
0
1
1
0
0
0
0
0
0
0
1
X
X
0
0
1
0
1
0
0
0
0
0
0
1
X
X
X
0
0
1
1
1
0
0
0
0
0
1
X
X
X
X
0
1
0
0
1
0
0
0
0
1
X
X
X
X
X
0
1
0
1
1
0
0
0
1
X
X
X
X
X
X
0
1
1
0
1
0
0
1
X
X
X
X
X
X
0
1
1
1
1
0
1
X
X
X
X
X
X
X
1
0
0
0
1
1
X
X
X
X
X
X
X
X
1
0
0
1
1
3-37.
I0
a) b)
S0
S1
S2
DECODER
0
1
2
A0
A1
A2
4x1 MUX
14
exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the
publisher.
X
X
X
X
X
X