Problem Solutions – Chapter 2
CHAPTER 2
© 2016 Pearson Education, Inc.
2-1.*
a)
XYZ X Y Z
Verification of DeMorgan’s Theorem
X
Y
Z
XYZ
XYZ
X Y Z
0
0
0
0
1
1
0
1
0
1
1
0
1
0
0
1
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
b)
( ) ( )X YZ X Y X Z
The Second Distributive Law
X
Y
Z
YZ
X + YZ
X + Y
X + Z
(X + Y)(X + Z)
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
c)
XY YZ XZ XY YZ XZ
X
Y
Z
XY
YZ
XZ
XY YZ XZ
XY
YZ
XZ
XY YZ XZ
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
0
0
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
1
0
1
0
1
1
0
0
1
0
0
1
0
1
0
0
0
0
0
2-2.*
Problem Solutions – Chapter 2
2
b)
AB BC AB BC
= 1
c)
Y XZ XY
=
X Y Z
Y XY XZ
d)
XY Y Z XZ XY YZ
=
XY XZ YZ
()
XY YZ X X XZ XY YZ
2-3.+
a)
ABC BCD BC CD
=
B CD
( ) ( )
ABC ABC BC BCD BCD CD
AB C C BC D D BC CD
Problem Solutions – Chapter 2
3
2-4.+
Given:
0, 1A B A B
2-5.+ Step 1: Define all elements of the algebra as four bit vectors such as A, B and C:
A = (A3, A2, A1, A0)
2-6.
a)
()AC ABC BC AC ABC ABC BC
(
AC ABC ABC BC
Problem Solutions – Chapter 2
4
2-7.* a)
( )( ) ( )( )( )XY XYZ XY X XYZ X XY X Z X X X Y X Z
( )( )X Y X Z X YZ
2-8.
a)
F ABC AC AB
b)
F ABC AC AB
2-9.*
a)
( )( )F A B A B
2-10.*
Truth Tables a, b, c
X
Y
Z
a
A
B
C
b
W
X
Y
Z
c
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
1
0
1
0
1
1
1
0
1
1
1
0
0
1
1
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
1
0
1
1
0
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
Problem Solutions – Chapter 2
a) Sum of Minterms:
XYZ XYZ XYZ XYZ
Product of Maxterms:
( )( )( )( )X Y Z X Y Z X Y Z X Y Z
2-11. a)
(1, 2, 4, 6) (0, 3, 5, 7),E m M
(0, 2, 4, 7) (1, 3, 5, 6)F m M
2-12.* a)
( )( )AB C B CD AB ABCD BC AB BC
s.o.p.
()B A C
p.o.s.
2-13.
B
D
A
A
Y
a)
b)
c)
Z
A
B
C
X
Y
Z
C
C
A
D
X
Y
Z
B
C
W
B
B
C
A
Problem Solutions – Chapter 2
6
2-14.
2-15.*
Y
B
a) b) c)
B
1
11
1 1 1 1
1
1
2-16.
W
X
Z
A
B
D
A
B
D
1
1
1
1
1
1
1
1
1
1
2-17.
W
X
Z
A
B
D
1
1
1
1
1
1
1
1
1
1
1
X
Z
A
C
X
Z
C
1
1
1
1
1
1
1
1
Y
B
Y
A
B
a)
b)
c)
d)
1
1
1
1
1
1
1
1
1
1
1
Y
C
C
a)
b)
c)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Y
C
a)
b)
1
1
1
1
1
1
Problem Solutions – Chapter 2
7
2-18.*
Y
C
a) b) c)
Y
1
11
2-19.*
2-20.
a)
, , , ,Prime BD ACD ABC ABC ACD
b)
, , , , ,Prime WY XY WXZ W X XYZ WYZ
2-21.
W
X
Z
A
B
D
0
0
0
0
0
0
0
0
2-22.*
a) s.o.p.
CD AC BD
b) s.o.p.
AC BD AD
c) s.o.p.
( )BD ABD ABC or ACD
Y
C
a)
b)
F
F
0
0
0
0
0
0
0
0
0
Problem Solutions – Chapter 2
8
2-23.
a) s.o.p.
ABD ABC ABD ABC
b) s.o.p.
X YZ WZ
2-24.
W
X
Z
A
C
1
1
1
1
X
X
X
X
A
B
D
1
1
1
1
X
X
X
X
X
X
2-25.*
Y
C
a) b) c)
B
1
1 1
1
XX
X X
2-26.
A
D
W
X
Z
0
0
1
0
X
0
1
X
X
X
X
1
0
X
X
1
1
0
0
X
W
Z
1
X
X
X
1
0
0
X
A
B
0
0
X
0
X
X
1
1
D
Y
a)
b)
c)
B
1
1
1
X
C
1
X
X
C
a)(1)
b)(1)
X
Y
X
0
1
X
0
X
X
a)(2)
b)(2)
X
0
0
1
Y
X
0
1
X
X
0
0
1
C
X
1
0
X
0
X
0
X
Problem Solutions – Chapter 2
9
2-27.*
X Y XY XY
2-28.
()ABCD AD AD ABCD A D
For this situation,
So, we can write
( , , , ) ( )F A B C D X Y ABCD A D
A
2-29.*
The longest path is from input
C or D.
Problem Solutions – Chapter 2
10
2-30.
a)
2-31.
PHL-C, D to F PLH PHL
PLH-C, D to F PHL PLH
a) t 2t 2 t 2(0.36) 2(0.20) 1.12 ns
t 2t 2t 2(0.20) 2(0.36) 1.12 ns
2-32.
If the rejection time for inertial delays is greater than the propagation delay, then an output change can occur before it
can be predicted whether or not it is to occur due to the rejection time.
Problem Solutions – Chapter 2
2-33.+
a) The propagation delay is
pd PHL PLH
max( 0.05, 0.10) 0.10 ns.t t t
Assuming that the gate is an inverter, for a positive output pulse, the following actually occurs:
a) The propagation delay istpd = max(tPHL = 0.05, tPLH = 0.10) = 0.10 ns.
Assuming that the gate is an inv erter, f or a positiv e output pulse, the f ollowing actually occurs:
a) The propagation delay istpd = max(tPHL = 0.05, tPLH = 0.10) = 0.10 ns.
b) For a negative output pulse, the following actually occurs:
b) For a negative output pulse, the following actually occurs:
b) For a negative output pulse, the following actually occurs:
2-34.*
X1
N1 N2
2-35.
— Figure 4-40: Structural VHDL Description
library ieee;
use ieee.std_logic_1164.all;
Problem Solutions – Chapter 2
architecture concurrent of nand2 is
begin
out1 <= not (in1 and in2);
end architecture;
architecture concurrent of nand3 is
begin
out1 <= not (in1 and in2 and in3);
end concurrent;
library ieee;
use ieee.std_logic_1164.all;
entity fig440 is
port(X: in std_logic_vector(2 to 0);
f: out std_logic);
end fig440;
architecture structural_2 of fig440 is
component NAND2
port(in1, in2: in std_logic;
out1: out std_logic);
end component;
0 2 1 0
F X X X X
F =X0X2 + X1X2
Problem Solutions – Chapter 2
13
2-36. begin
g0: NOT_1 port map (D, x1);
X D BC
g1: AND_2 port map (B, C, x2);
Y ABCD
X = D + BC
Y = A BCD
begin
g0: NOT_1 port map (D, x1);
g1: AND_2 port map (B, C, x2);
g2: NOR_2 port map (A, x1, x3);
2-37.
f
a
b
c
a
2-38.* begin
2-39.*
X1
N1 N2
Problem Solutions – Chapter 2
14
2-40.
module circuit_4_50(A, B, C, D, X, Y);
input A, B, C, D;
output X, Y;
or g5(n5, n1, n2);
nor
g6(n3, n1, A);
endmodule
Problem Solutions – Chapter 2
2-41.
module circuit_4_51(X, F);
input [2:0] X;
output F;
module circuit_4_51(X, F);
input [2:0] X;
output F;
2-42.
a
b
a
2-43.*