Problem Solutions – Chapter 12
CHAPTER 12
12-1.
Binary
a
b
c
54
0010 1 01 00
M
M
58
0010 1 10 00
M
M
1000 0 01 00
M
M
0010 1 11 00
M
M
0111 1 00 00
M
M
64
0011 0 01 00
M
M
54
H
H
58
0010 1 10 00
H
H
1000 1 00 00
M
M
60
0011 0 00 00
H
H
0111 1 00 00
M
H
12-2.
Binary
a
b
20
0010 0000
M
M
04
0000 0100
M
M
28
0010 1000
M
M
M
04
0000 0100
H
28
0010 1000
H
H
0001 1100
M
M
M
10
0001 0000
M
M
M
10
0001 0000
M
H
60
0110 0000
M
H
M
70
0111 0000
M
H
M
Problem Solutions – Chapter 12
2
12–3*.
Since the lines are 32 bytes, 5 bits are used to address bytes in the lines.
Since there are 1K bytes, there are 1024/32 = 25 cache lines.
12–4.
(a) Number of rows = 1M/(4 bytes/line 4 words/line lines/set) = 215 = 32,768
The number of bits for addressing the word and byte within a line is 4 bits.
12-5.*
a) See Instruction and Data Caches section on page 636 of the text.
12–6.
12–7.*
000000 00 00 (i0)
000001 00 00 (i4)
000001 10 00 (i6)
000010 10 00 (i10)
000000 01 00 (i1)
000011 00 00 (d)
00001 11 00 (i7)
000011 10 00 (d)
000000 10 00 (i2)
000001 01 00 (i5)
000010 00 00 (i8)
000010 11 00 (i11)
000011 01 00 (d)
000011 11 00 (d)
12–8.
The use of write-allocate with a write-through cache defeats the purpose of write-allocate. The idea behind write-allocate is
Problem Solutions – Chapter 12
3
12-9
a) Number of sets = 1K/(4 
12–10.
12–11.*
a) Effective Access Time = 0.91 * 4ns + 0.09 * 40 ns = 7.24 ns
12–12.
a) Effective Access Time = 0.91 * 1ns + 0.09 * 20 ns = 2.71 ns
4
12–13.
Tag
Index Tag
Data
Tag Memory
Address bus
CPU Main Memory
Data
Hit/Miss
Tag
12–14.+
Index Tag
Address bus
CPU Main
Word
Cache Data Bus
32
128
1612 2
Memory
32 32 32 32 32 32 32 32
Main
Memory
Write
Word
a)
Problem Solutions – Chapter 12
Cache
Read
Write
Hit 0
Read M0
Read M1
Read Mem
Read Main Mem
All cases are the same as the read misses with the exception that the new v alue is then writen to
the cache and the dirty bit is set f or all cases.
12–15.*
a) Each page table handles 512 pages assuming 64-bit words. There are 4263 pages which
12–16.
a) With a page size of 4KB, then the page offset is 12 bits
12–17.
(a) Miss – Address not in cache
12–18.
32-bit word implies 4 bytes/word
(a) 4K byte pages implies 12 bit offset which implies 20 bit tags. With 32 entries, associative memory = 32 × 20 = 320 bits.
12–19.
Directory pages = 4
Problem Solutions – Chapter 12
Pages Program 2 5670/1024 = 6
12-20.*
In section 12-3, it is mentioned that write-through in caches can slow down processing, but this can be avoided by
12–21.
If locality of reference did not exist, no benefits would be gained by either virtual memories or caches. Without locality