Problem Solutions – Chapter 11
CHAPTER 11
11-1*
Heads × (cylinders/Head) × (sectors/cylinder) × (1 cylinder/track) × (bytes/sector)
11-2.
8.5 msec + 4.17 msec + 0 msec + ((1 sec/(100 Mbytes)) × 1Mbytes)=22.67 ms
11–3.
Pixels
Subpixels
5,770,000
6,912,000
11–4.
(CA)16 = (1100 1010)2 RS1 = 1 RS0 = 0
11-5.*
a) If each address line is used for a different CS input, there will be no way to address
11–6.
#
Port A ADRS
Control ADRS
1
0000 0001
1000 0001
3
0000 0100
0100 0100
1000 0100
1100 0100
4
0000 1000
0100 1000
1000 1000
1100 1000
Problem Solutions – Chapter 11
2
11-7.*
A given address can be shared by two registers if one is write only and one is read only. If a register
is both written to and read from the bus, then it needs its own address. An 8-bit address provides
11–8.
CPU Data Bus
I/O Data Bus
I/O Data
STB
DATA
11-9.*
Data Bus
Data bus
From I/O
Read Operation
(a) (b)
11–10.
Data Bus
Address Bus
Data bus
Address bus
From I/O
Read Operation
Problem Solutions – Chapter 11
3
11-11.*
11–12.
0 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 0 0 0 1 1
(a)
11-13.*
SYNC
8 bits Address
Dev ice
Check
4 bits
01101001
4 bits
Type
0100111
Endpoint
Address
0010
EOP
CRC
11–14.
SYNC
8 bits Address
Device
Check
4 bits
01101001
4 bits
Type
0100111
Endpoint
Address
0010
EOP
CRC
11–15.
Interrupt-initiated data transfer permits the action required by an interrupt to occur anywhere within the programs
11-16.*
Device 0
Device 1
Device 2
Description
PI
PO
RF
VAD
PI
PO
RF
VAD
PI
PO
RF
VAD
Initially
0
0
0
–
0
0
0
–
0
0
1
–
0
0
1
–
0
0
0
–
0
0
1
–
11–17.
The interrupt service routine polls the devices connected to the common interrupt line. The first device checked has the highest
priority. The priority of the other devices corresponds to when they are checked.
11-18.*
11–19.
11-20.*
This is Figure 13-17 with the Interrupt and Mask Registers increased
Problem Solutions – Chapter 11
5
11–21.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A4
A3
A2
A1
V
1
0
W
X
Y
Z
0
1
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
1
1
1
1
0
1
1
1
1
0
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
1
0
1
1
0
1
1
1
0
0
1
11-22.*
When the CPU communicates with the DMA, the read and write lines are used
11–23.
a) CPU initiates DMA by transferring the following:
2048 to the word count register.
4096 to the DMA address register.
b) 1) I/O Device sends the DMA controller a “DMA request.”
0
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
0
1
1
1
0
1
1
0
1
0
1
0
0
0
1
x
x
x
x
x
x
x
x
x
x
x
x
1
1
0
0
1
1
0
1
1
0
0
0
1
0
0
0
0
1
x
x
x
x
x
x
x
x
x
x
x
1
0
1
1
1
1
0
1
0
1
1
0
1
0
0
0
0
0
1
x
x
x
x
x
x
x
x
x
x
1
0
1
0
1
1
0
1
0
1
0
0
1
0
0
0
0
0
0
1
x
x
x
x
x
x
x
x
x
1
0
0
1
1
1
0
1
0
0
1
0
1
0
0
0
0
0
0
0
1
x
x
x
x
x
x
x
x
1
0
0
0
1
1
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
x
x
x
x
x
x
x
0
1
1
1
1
1
0
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
1
x
x
x
x
x
x
0
1
1
0
1
1
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
x
x
x
x
x
0
1
0
1
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
x
x
x
x
0
1
0
0
1
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
x
x
x
0
0
1
1
1
1
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
x
x
0
0
1
0
1
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
x
0
0
0
1
1
1
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
0
–
–
–
–
–
–
–
–