Problem Solutions – Chapter 10
1
CHAPTER 10
© 2016 Pearson Education, Inc.
10–1.
a) Maximum frequency = 1/pipe stage delay = 1/0.8 ns = 1.25 GHz.
10-2.*
a) The latency time = 0.5 ns × 8 = 4.0 ns.
10–3.
PC
IR
Data A
Data B
Data F
Reg
N
X
X
X
X
X
N+1
LDI R1, 1
X
X
X
X
N+2
LDI R2, 2
–1
1
X
X
N+3
LDI R3, 3
–1
2
1
X
N+4
LDI R4, 4
N+5
LDI R5, 5
–1
4
3
R2 = 2
N+6
LDI R6, 6
–1
5
4
R3 = 3
N+7
LDI R7, 7
N+8
X
–1
7
6
R5 = 5
N+9
X
X
X
7
R6 = 6
X
X
X
X
10–4.
Register Indirect: Load, Store, JMR
10–5.
Problem Solutions – Chapter 10
2
10-6.*
Cycle 1: PC = 10F
10–7.
Cycle 1: IF PC = 10F
10–8.
Cycle 1: PC = 10F
10–9.
Cycle 1: PC = 10F
10-10.+
Answer not given; varies depending on synthesis software used.
10–11.*
MOVA R7, R6
Problem Solutions – Chapter 10
3
10-12.
SUB R7, R7, R2
BNZ R7, 000F
10–13*
a)
MOV R7,R6
a)
IF DOF EX WB
1 2 3 4 5 6 7
AND R8,R8,R7
1 2 3 4 5 6 7
b)
b)
SUB R7,R7,R2
NOP
a)
IF DOF EX WB
1 2 3 4 5 6 7
MOV R7,R6
IF DOF EX WB
1 2 3 4 5 6 7
SUB R7,R7,R2
b)
10–14.
IF DOF EX WB
1 2 3 4 5 6 7
IF DOF EX WB
1 2 3 4 5 6
MOV R7,R6
IF
DOF
EX
WB
SUB
R7, R7, R2
1
2
3
4
5
6
7
Control Hazards
IF
DOF
EX
WB
OR R4, R8, R2
AND
R8, R7, R4
IF
EX
WB
Data Hazards
Problem Solutions – Chapter 10
4
10–15.
Time Cycle 1
IF
PC: 0000 0001
DOF
PC−1: XXXXXXXX
IR: XXXXXXXX
IF
PC: 0000 0002
DOF
PC−1: 0000 0002
IR: 0A73 8800
PC−2: XXXXXXXX
A: XXXXXXXX
B: XXXXXXXX
RW: X
DA: XX
MD: X
BS: X
PS: X
MW: X
FS: X
MB: X
CS: X
WB
D0: : XXXXXXXX
D1: XXXXXXXX
D2: XXXXXXXX
RW: X
DA: XX
MD: X
Time Cycle 3
IF
PC: 0000 0003
DOF
PC-1: 0000 0003
IR: 9003800F
PC-2: 0000 0002
A: 0000 0030
B: 0000 0010
RW: 1
DA: 07
MD: 0
BS: 0
PS: X
MW: 0
FS: 5
MB: 0
CS:X
D0: XXXXXXXX
D1: XXXXXXXX
D2: XXXXXXXX
RW: X
DA: XX
MD: X
Time Cycle 4
IF
PC: 0000 0003
DOF
PC−1: 0000 0003
IR: 9003 800F
PC−2: 0000 0002
A: 0000 0030
B: XXXXXXXX
RW: 0
DA: 00
MD: X
BS: 0
MW: 0
FS: 0
MB: 1
CS: X
D0: 0000 0020
D1: XXXXXXXX
D2: 0000 0000
RW: 1
DA: 07
MD: X
Time Cycle 5
IF
PC: 0000 0004
R7: 0000 0020
DOF
PC-1: 0000 0004
IR: 1083 9000
PC-2: 0000 0003
A: 0000 0020
B: XXXXXXXX
RW: 0
DA: 00
MD: X
BS: 1
MW: 0
FS: 0
MB: 1
CS: X
WB
D0: 0000 0030
D1: XXXXXXXX
D2: 0000 0000
RW: 0
DA: 00
MD: X
PC: 0000 0012
Time Cycle 6
IF
PC: 0000 0012
DOF
PC-1: 0000 0004
IR: 12440800
PC-2: 0000 0003
A: 0000 0020
B: 0000 0020
RW: 1
DA: 08
MD: 0
BS: 0
MW: 0
FS: 8
MB: 0
CS: X
WB
D0: 0000 0020
D1:XXXXXXXX
D2: 0000 0000
RW: 0
DA: 00
MD: X
Time Cycle 7
IF
PC: 0000 0012
DOF
PC-1: 0000 0004
IR: 12440800
PC-2: 0000 0004
A: XXXXXXXX
B: 0000 0010
RW: 0
DA: 00
MD: 0
BS: 0
MW: 0
FS: 8
MB: 0
CS: X
WB
D0: 0000 0020
D1: XXXXXXXX
D2: 0000 0000
RW: 1
DA: 08
MD: 0
Time Cycle 8
IF
PC: 0000 0013
R8: 0000 0020
DOF
PC-1: 0000 0013
IR: XXXXXXXX
PC-2: 0000 0004
A: 0000 0020
B: 0000 0010
RW: 1
DA: 04
MD: 0
BS: 0
PS: X
MW: 0
FS: 9
MB: 0
CS: X
WB
D0: XXXXXXXX
D1: XXXXXXXX
D2: XXXXXXXX
RW: 0
DA: 00
MD: 0
Time Cycle 9
IF
PC: 0000 0014
DOF
PC-1: 0000 0014
IR: XXXXXXXX
PC-2: 0000 0013
A: XXXXXXXX
B: XXXXXXXX
RW: X
DA: XX
MD: X
BS: X
PS: X
MW: X
FS: X
MB: 0
CS: X
D0: 0000 0020
D1: XXXXXXXX
D2: 0000 0000
RW: 1
DA: 04
MD: 0
Time Cycle 10
IF
R4:
0000 0020
PC−2: XXXXXXXX
A: XXXXXXXX
B: XXXXXXXX
RW: X
DA: XX
MD: X
BS: X
PS: X
MW: X
FS: X
MB: X
CS: X
D0: XXXXXXXX
D1: XXXXXXXX
D2: XXXXXXXX
RW: X
DA: XX
MD: X
Time Cycle 2
Problem Solutions – Chapter 10
5
10–16.*
Time Cycle 1
IF
PC: 0000 0001
Time Cycle 2
IF
PC: 0000 0002
IR: 0A73 8800
WB
D0: XXXXXXXX
D1:XXXXXXXX
D2:XXXXXXXX
RW:X
DA:XX
MD:X
Time Cycle 3
IF
PC: 0000 0003
DOF
IR: 9003 800F
D0: XXXXXXXX
D1:XXXXXXXX
D2:XXXXXXXX
RW:X
DA:XX
MD:X
Time Cycle 4
IF
PC: 0000 0004
DOF
PC-1:0000 0004
IR:1083 9000
WB
D0: 0000 0020
D1:XXXX XXXX
RW:1
DA:07
MD: 0
PC: 0000 0012
Time Cycle 5
IF
PC: 0000 0013
R7: 0000 0020
DOF
PC-1: 0000 00013
IR: 1244 0800
WB
D0: 0000 0020
D1: XXXXXXXX
D2: 0000 0000
RW: 0
DA: 00
MD: 0
Time Cycle 6
IF
PC: 0000 0014
DOF
PC-1: 0000 0014
IR: XXXX XXXX
WB
D0: 0000 0010
D1: XXXX XXXX
D2: 0000 0000
RW: 1
DA: 08
MD: 0
IF
PC: 0000 0014
R7: 0000 0020
DOF
PC-1: 0000 0014
IR: XXXX XXXX
D1: XXXX XXXX
D2: 0000 0000
RW: 1
DA: 04
MD:0
R4: 0000 0010
exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
IR: XXXXXXXX
WB
D0: XXXXXXXX
D1:XXXXXXXX
D2:XXXXXXXX
RW:X
DA:XX
MD:X
Problem Solutions – Chapter 10
6
10–17.
10–18.
D0
0
C31
D0
C14
D0
C9
IM9
0
D0
C7
D0
C0
IM0
IM7
10–19.*
D0
AA3:0
FAA3:0
D0
DA3:0
FBA3:0
D0
BA3:0
FDA3:0
IF
DOF
EX
WB
1
2
3
4
5
6
7
DOF
DOF
DOF
Problem Solutions – Chapter 10
7
10–20.
MZ0
MZ1
MZ-10
MZ-1
1MI PS Z
Problem Solutions – Chapter 10
10–21.
(a) Branch if overflow
R
M
P
M
L
M
Action
Address
MZ
CA
W
DX
D
BS
S
W
F S
C
MA
B
AX
BX
CS
R31 CC 00001
BOV0
01
01
1
1F
0
00
0
0
8
0
10
1
00
00
11
BOV1
01
00
0
00
00
0
0
0
00
00
00
00
BOV3
01
00
0
00
00
0
0
0
00
00
00
00
BOV4
00
0
00
00
0
0
0
0
00
00
00
00
(b) Branch if greater than zero
R
M
P
M
L
M
Action
Address
MZ
CA
W
DX
D
BS
S
W
F S
C
MA
B
AX
BX
CS
R31 CC 11000
BLZ0
01
04
1
1F
0
00
0
0
8
0
10
1
00
00
11
BLZ1
01
00
0
00
00
0
0
0
00
00
00
00
BLZ4
00
0
00
00
0
0
0
0
00
00
00
00
(c) Compare Less Than
R
M
P
M
L
M
Action
Address
MZ
CA
W
DX
D
BS
S
W
F S
C
MA
B
AX
BX
CS
RSA– RSB
CC L Z N C V
CGT0
01
00
0
00
0
00
0
0
5
1
00
0
00
00
00
MCMC + 1 (NOP)
CGT1
01
00
0
00
0
00
0
0
0
0
00
0
00
00
00
CGT2
01
18
1
1F
0
00
0
0
8
0
10
1
00
00
11
MCMC + 1 (NOP)
CGT3
01
00
0
00
0
00
0
0
0
0
00
0
00
00
00
MCMC + 1 (NOP)
CGT5
01
00
0
00
0
00
0
0
0
0
00
0
00
00
00
CGT6
01
00
0
00
0
11
0
0
0
0
01
1
00
00
10
CGT7
10
IDLE
0
00
0
00
0
0
0
0
00
0
00
00
00
Problem Solutions – Chapter 10
9
10–22.
(a) Push
R
M
P
M
L
M
Action
Address
MZ
CA
W
DX
D
BS
S
W
FS
C
MA
B
AX
BX
CS
RDRRSA+ 1
PUSH0
01
01
1
01
0
00
0
0
2
0
00
1
00
00
11
(b) Pop
R
M
P
M
L
M
Action
Address
MZ
CA
W
DX
D
BS
S
W
FS
C
MA
B
AX
BX
CS
RSBRSA– 1
10–23.*
(a) Add with carry
R
M
P
M
L
M
Action
Address
MZ
CA
W
DX
D
BS
S
W
FS
C
MA
B
AX
BX
CS
R31 CC 00010
AWC0
01
02
1
1F
0
00
0
0
8
0
10
1
00
00
11
RDRR16 + 1
AWC4
01
01
1
0
00
0
0
2
0
00
1
10
00
11
AWC5
00
IDLE
0
0
00
0
0
0
0
00
0
00
00
00
(a) Subtract with borrow
R
M
P
M
L
M
Action
Address
MZ
CA
W
DX
D
BS
S
W
FS
C
MA
B
AX
BX
CS
R31 CC 00010
SWB0
01
02
1
1F
0
00
0
0
8
0
10
1
00
00
11
RDRR16 – 1
SWB4
01
01
1
0
00
0
0
5
0
00
1
10
00
11
SWB5
00
0
0
00
0
0
0
0
00
0
00
00
00
PUSH1
01
00
0
00
0
00
0
0
0
0
00
0
00
00
00
PUSH2
01
00
0
01
0
00
0
1
0
0
00
0
00
00
00
PUSH3
00
0
00
0
00
0
0
0
0
00
0
00
00
00
Problem Solutions – Chapter 10
10
10–24.
(a) Add Memory Indirect
R
M
P
M
L
M
Action
Address
MZ
CA
W
DX
D
BS
S
W
FS
C
MA
B
AX
BX
CS
AMI0
01
00
1
10
1
00
0
0
0
0
00
0
00
00
00
E
(b) Add to memory
R
M
P
M
L
M
Action
Address
MZ
CA
W
DX
D
BS
S
W
FS
C
MA
B
AX
BX
CS
R16 MRSA
ATM0
01
00
1
10
1
00
0
0
0
0
00
0
00
00
00
ATM1
01
00
0
00
0
00
0
0
0
0
00
0
00
00
00
R16 R16 + RSB
ATM2
01
00
1
10
0
00
0
0
2
0
00
0
10
00
00
ATM3
01
00
0
00
0
00
0
0
0
0
00
0
00
00
00
01
00
0
01
0
00
0
1
0
0
00
0
10
00
00
ATM5
00
0
00
0
00
0
0
0
0
00
0
00
00
00
10–25.*
Memory Scalar Add (Assume R[SB] > 0 to simplify coding)
R
M
P
M
L
M
Action
Address
MZ
CA
W
DX
D
BS
S
W
FS
C
MA
B
AX
BX
CS
R16 RSB
MSA0
01
00
1
10
0
00
0
0
0
0
00
0
00
00
00
R18 R0
MSA1
01
00
1
12
0
00
0
0
0
0
00
0
00
00
00
R16 R16 – 1
MSA2
01
01
1
10
0
00
0
0
5
0
00
1
10
00
11
MCMC + 1 (NOP)
MSA3
01
00
0
00
0
00
0
0
0
0
00
0
00
00
00
R17 RSA+ R16
MSA4
01
00
1
11
0
00
0
0
2
0
00
0
00
10
00
MSA5
01
00
0
00
0
00
0
0
0
0
00
0
00
00
00
R18 MR17+ R18
MSA7
01
00
1
12
1
00
0
0
0
0
00
0
11
12
00
MSA8
01
00
1
01
0
00
0
0
0
0
00
0
11
00
00
MSA9
00
0
00
0
00
0
0
0
0
00
0
00
00
00
AMI1
01
00
0
00
0
00
0
0
0
0
00
0
00
00
00
AMI2
01
00
1
10
1
00
0
0
0
0
00
0
10
00
00
AMI3
01
00
0
00
0
00
0
0
0
0
00
0
00
00
00
AMI4
01
00
1
01
0
00
0
0
2
0
00
0
00
10
00
AMI5
00
0
00
0
00
0
0
0
0
00
0
00
00
00
Problem Solutions – Chapter 10
11
10–26.
Memory Vector Add (Assume R[SB] > 0 to simplify coding)
R
M
P
M
L
M
Action
Address
MZ
CA
W
DX
D
BS
S
W
FS
C
MA
B
AX
BX
CS
R16 RSB
MVA0
01
00
1
10
0
00
0
0
0
0
00
0
00
00
00
MCMC + 1 (NOP)
MVA1
01
00
0
00
0
00
0
0
0
0
00
0
00
00
00
R16 R16 – 1
MVA2
01
01
1
10
0
00
0
0
5
0
00
1
10
00
11
MCMC + 1 (NOP)
MVA3
01
00
0
00
0
00
0
0
0
0
00
0
00
00
00
10–27.
(a)
RDR(RSA31:24+ RSB31:24,
10–28.
(a) For 16-bit words, the operation can produce a 128-bit result containing 128/16 = 8 minimum words.
R18 R16 + RDR
MVA5
01
00
1
12
0
00
0
0
2
0
00
0
10
00
00
R19 MR17
MVA6
01
00
1
13
1
00
0
0
0
0
00
0
11
00
00
MVA7
01
00
1
14
1
00
0
0
0
0
00
0
12
00
00
R21 R19 + R20
MVA9
01
00
1
15
0
00
0
0
2
0
00
0
13
14
00
MVA11
01
00
0
01
0
00
0
1
0
0
00
0
12
15
00
00
0
00
0
00
0
0
0
0
00
0
00
00
00