Problem 8-6
module RAM_static (output data_out, input data_in, CS_b, WE_b);
// Note: chip select and write are active-low
Problem 8-7
module ALU_4_bit (output reg [4: 0] Alu_out, input [3: 0] Data_A, Data_B, input [2: 0] Opcode);
parameter Add = 3’b000;
parameter Sub = 3’b001;
always @ (Data_A, Data_B, Opcode) begin
Alu_out = 5’b0;
case (Opcode)
Add: Alu_out = Data_A + Data_B;
Sub: Alu_out = Data_A – Data_B;
Rand_B: Alu_out = & Data_B;
endcase
end
endmodule
module Toggle_Button (output Load, Led_idle, Led_wait, Led_rdy, input Go, clk, reset);
reg [1: 0] state, next_state;
parameter S_idle = 2’b00, S_1 = 2’b01, S_2 = 2’b10, S_3 = 2’b11;
assign Led_rdy = (state == S_3);
always @ (posedge clk) if (reset) state <= S_idle; else state <= next_state;
always @ (Go, clk) begin
next_state = S_idle;
case (state)
S_idle: if(reset) next_state = S_idle; else next_state = Go ? S_1: S_idle;
S_1: next_state = S_2;
S_2: next_state = Go ? S_2: S_3;
S_3: next_state = Go ? S_1: S_3;
output [4: 0] Alu_out,
output Led_idle, Led_wait, Led_rdy,
input [3: 0] Data,
input [2: 0] Opcode,
input Go,
input clk, reset
);
wire [3: 0] Reg_out; // Note: Must size the bus connecting M1 and M2
module t_ALU_machine_4_bit ();
wire [4: 0] Alu_out;
wire Led_idle, Led_wait, Led_rdy;
wire clk;
reg Go, reset;
reg [3: 0] Data;
reg [2: 0] Opcode;
parameter Add = 3’b000;
initial #500 $finish;
initial fork
reset = 0;
#10 reset = 1;
#20 reset = 0;
Go = 0;
#250 Go = 1;
#200 Go = 0;
#50 Opcode = 0;
#150 Opcode = 1;
module Clock_Prog (output reg clock);
parameter Latency = 100;
parameter Pulse_Width = 50;
parameter Offset = 50;
Problem 8-8
module Counter8_Prog (
output reg [7: 0] count, input [1: 0] mode, input direction, enable, clk, reset);
parameter start_count = 1; // Sets initial pattern of the display to LSB of
count
// Mode of count
parameter binary = 0;
always @ (posedge clk or posedge reset)
if (reset ==1) count <= start_count;
else if (enable ==1)
case (mode)
binary: count <= binary_count (count, direction);
ring1: count <= ring1_count (count, direction);
function [7: 0] ring1_count;
input [7: 0] count;
input direction;
begin
default: if (direction == left) ring2_count = {count [5:0], count[7: 6]};
else ring2_count = {count[1: 0], count[7: 2]};
endcase
end
endfunction
function [7: 0] jump2_count;
input [7: 0] count;
// Other functions are declared here.
endmodule
module t_Counter8_Prog ();
wire [7: 0] count;
reg [1: 0] mode;
reg direction, enable, clk, reset;
// Mode of count
parameter binary = 0;
Counter8_Prog M0 (count, mode, direction, enable, clk, reset);
initial #1500 $finish;
initial begin clk = 0; forever #5 clk = ~clk; end
initial fork
#10 reset = 0; #20 reset = 1; #40 reset = 0;
#150 direction = right;
#300 mode = ring1;
#300 direction = left;
#400 direction = right;
#500 mode = ring2;
Problem 8-9
`timescale 1ns / 10ps
module SRAM_with_Con # (parameter word_size = 8, addr_size = 11)(
module SRAM_Con (output reg Rdy, CS_b, OE_b, WE_b, input ADS_b, R_W, clk, reset);
parameter
S_idle = 0,
always @ (posedge clk)
if (reset == 1) state <= S_idle;
else state <= next_state;
always @ (state, ADS_b, R_W) begin
OE_b = 1; // Active-low
CS_b = 1;
WE_b = 1;
Rdy = 0;
next_state = S_idle;
case (state)
S_idle: if ((ADS_b == 0) && (R_W == 1)) next_state = S_Rd1;
else if ((ADS_b == 0) && (R_W == 0)) next_state = S_Wr1;
S_Rd1: next_state = S_Rd2;
endcase
end
endmodule
module SRAM # (parameter
word_size = 8,
addr_size = 11,
reg [word_size-1 : 0] data_int;
reg [word_size-1 : 0] RAM_col0 [mem_depth-1 :0];
reg [word_size-1 : 0] RAM_col1 [mem_depth-1 :0];
reg [word_size-1 : 0] RAM_col2 [mem_depth-1 :0];
wire [col_addr_size-1: 0] col_addr = addr[col_addr_size-1: 0];
wire [row_addr_size-1: 0] row_addr = addr[addr_size-1: col_addr_size];
assign data = ((CS_b == 0) && (WE_b == 1) && (OE_b == 0))
? data_int: Hi_Z_pattern;
always @ (data, col_addr, row_addr, CS_b, OE_b, WE_b)
begin
data_int = Hi_Z_pattern;
if ((CS_b == 0) && (WE_b == 0)) // Priority write to memory
case (col_addr) // column address
0: RAM_col0[row_addr] = data;
1: RAM_col1[row_addr] = data;
2: RAM_col2[row_addr] = data;
3: RAM_col3[row_addr] = data;
else if ((CS_b == 0) && (WE_b == 1) && (OE_b == 0)) // Read from memory
case (col_addr)
0: data_int = RAM_col0[row_addr];
1: data_int = RAM_col1[row_addr];
2: data_int = RAM_col2[row_addr];
3: data_int = RAM_col3[row_addr];
4: data_int = RAM_col4[row_addr];
endcase
end
///* Comment out of the model for a zero delay functional test.
specify
// Parameters for the read cycle
specparam t_RC = 10; // Read cycle time
specparam t_AA = 8; // Address access time
// Parameters for the write cycle
specparam t_WC = 7; // Write cycle time
specparam t_CW = 5; // Chip select to end of write
specparam t_AW = 5; // Adress valid to end of write
//Module path timing specifications
(addr *> data) = t_AA; // Verified in simulation
(CS_b *> data) = (t_ACS, t_ACS, t_CHZ);
(OE_b *> data) = (t_OE, t_OE, t_OHZ); // Verified in simulation
//Timing checks (Note use of conditioned events for the address setup,
//depending on whether the write is controlled by the WE_b or by CS_b.
//Address setup before write enabled
$setup (addr, negedge WE_b &&& CS_b == 0, t_AS);
$setup (addr, negedge CS_b &&& WE_b == 0, t_AS);
//Width of write pulse
$width (negedge WE_b, t_WP);
endspecify
//*/
endmodule
module test_SRAM_with_Con ();
parameter word_size = 8;
parameter addr_size = 11;
wire [row_addr_size -1: 0] row_address = row;
wire [addr_size -1: 0] addr = {row_address, col_address};
// Three-state, bi-directional bus
initial #stop_time $finish;
initial begin reset = 1; #1 reset = 0; end
initial begin
#0 clk = 0;
forever #10 clk = ~clk;
end
for (row = 0; row <= mem_depth-1; row = row + 1) begin
@ (negedge clk);
@ (negedge clk);
end
end
end
// Non-Zero delay test: Read back walking ones from memory
initial begin
#latency;
ADS_b = 1;
end
end
0: write_probe = M1.M1.RAM_col0[M1.M1.row_addr];
1: write_probe = M1.M1.RAM_col1[M1.M1.row_addr];
2: write_probe = M1.M1.RAM_col2[M1.M1.row_addr];
3: write_probe = M1.M1.RAM_col3[M1.M1.row_addr];
4: write_probe = M1.M1.RAM_col4[M1.M1.row_addr];
endmodule
`timescale 1ns / 10ps
module SRAM_with_Con # (parameter word_size = 8, addr_size = 11)(
inout [word_size -1: 0] data,
input [addr_size -1: 0] addr,
output Rdy,
input ADS_b, R_W,
input clk, reset
);
always @ (posedge clk)
if (reset == 1) state <= S_idle;
else state <= next_state;
S_Rd1: next_state = S_Rd2;
S_Rd2: begin Rdy = 1; CS_b = 0; OE_b = 0; next_state = S_idle; end
S_Wr1: next_state = S_Wr2;
S_Wr2: begin CS_b = 0; WE_b = 0; next_state = S_Wr3; end
S_Wr3: begin Rdy = 1; next_state = S_idle; end
default: begin
next_state = S_idle;
OE_b = 1; // active low
CS_b = 1;
WE_b = 1;
end
endcase
end
endmodule
module SRAM # (parameter
word_size = 8,
reg [word_size-1 : 0] data_int;
reg [word_size-1 : 0] RAM_col0 [mem_depth-1 :0];
reg [word_size-1 : 0] RAM_col1 [mem_depth-1 :0];
reg [word_size-1 : 0] RAM_col2 [mem_depth-1 :0];
reg [word_size-1 : 0] RAM_col3 [mem_depth-1 :0];
reg [word_size-1 : 0] RAM_col4 [mem_depth-1 :0];
reg [word_size-1 : 0] RAM_col15 [mem_depth-1 :0];
assign data = ((CS_b == 0) && (WE_b == 1) && (OE_b == 0))
? data_int: Hi_Z_pattern;
always @ (data, col_addr, row_addr, CS_b, OE_b, WE_b)
begin
data_int = Hi_Z_pattern;
if ((CS_b == 0) && (WE_b == 0)) // Priority write to memory
case (col_addr) // column address
0: RAM_col0[row_addr] = data;
1: RAM_col1[row_addr] = data;
else if ((CS_b == 0) && (WE_b == 1) && (OE_b == 0)) // Read from memory
case (col_addr)
0: data_int = RAM_col0[row_addr];
1: data_int = RAM_col1[row_addr];
2: data_int = RAM_col2[row_addr];
3: data_int = RAM_col3[row_addr];
4: data_int = RAM_col4[row_addr];
endcase
end
///* Comment out of the model for a zero delay functional test.
specify
// Parameters for the read cycle