Chapter 5 Verify operations for data read from registers

Problem 5-25

module Prob_5_25 (output reg [7:0] count, input clk, rst_b);

parameter s0 = 0, s1 = 1, s2 = 2, s3 = 3, s4 = 4, s5 = 5, s6 = 6, s7 = 7, s8 = 8,

s9 = 9, s10 = 10, s11 = 11, s12 = 12, s13 = 13, s14 = 14, s15 = 15,

s16 = 16, s17 = 17;

reg [4: 0] state, next_state;

0: begin next_state = s1; count = 8’b0000_0001; end

1: begin next_state = s2; count = 8’b0000_0001; end

2: begin next_state = s3; count = 8’b0000_0001; end

3: begin next_state = s4; count = 8’b0000_0001; end

4: begin next_state = s5; count = 8’b0000_0010; end

5: begin next_state = s6; count = 8’b0000_0100; end

6: begin next_state = s7; count = 8’b0000_1000; end

7: begin next_state = s8; count = 8’b0001_0000; end

8: begin next_state = s9; count = 8’b0010_0000; end

9: begin next_state = s10; count = 8’b0100_0000; end

// Test plan:

// Simulate counting with power-up reset and reset-on-the-fly.

module t_Prob_5_25 ();

wire [7:0] count;

reg clk, rst_b;

Problem 5-26 (Three versions)

// Problem 5-26 Three versions

// Note: the issue of flushing A and C is dealt with by the datapath unit

// in version c.

module Problem_5_26 (

output [7: 0] A, B, C,

input F1, F2, Go, clock, rst

);

reg [1: 0] state, next_state;

parameter S_idle = 0, S_1 = 1, S_2 = 2;

always @ (posedge clock) if (rst) state <= S_idle;

else state <= next_state;

flush_A_C = 0;

incr_A = 0;

set_B = 0;

set_C = 0;

flush_B = 0;

next_state = S_idle;

case (state)

//module datapath_unit (A, B, C, flush_A_C, incr_A, set_B, set_C, flush_B, //clock); // version a, b

module datapath_unit ( // version c:

output reg [7: 0] A, B, C,

//input flush_A_C, incr_A, set_B, set_C, flush_B, clock;// a & b

input flush_A_C, incr_A, set_B, set_C, flush_B, clock, rst

);

always @ (posedge clock) begin

if (incr_A) A <= A+1;

if (set_B) B <= 1;

if (set_C) C <= 1;

if (flush_A_C) begin A <= 0; C <= 0; end

if (flush_B) B <= 0;

end

*/endmodule

module t_Problem_5_26 ();

wire [7: 0] A, B, C;

reg F1, F2, Go, clock, rst;

Problem_5_26 M0 (A, B, C, F1, F2, Go, clock, rst);

initial #700 $finish;

initial begin clock = 0; forever #5 clock = ~clock; end

initial fork

Version a: Incomplete event control expression. Note that reset on-the-fly with Go

already asserted does not launch new activity because the event control expression does

Version b: Complete event control expression (includes rst). Note that the state returns to

the idle state with reset on-the-fly, and the new activity is launched when rst de-asserts

Version c: Event control expression is complete, and rst is removed from the next-state logic.

Note that the machine returns to the idle state when rst is asserted, and that new activity is

Problem 5-27

module Problem_5_27 (

output reg [8: 0] alu_out,

input [7: 0] a, b,

input c_in,

input [2: 0] opcode

);

parameter [2: 0] add = 0;

always @ (a, b, c_in, opcode)

case (opcode)

add: alu_out = a + b + c_in;

subtract: alu_out = a + (~b) + c_in;

subtract_a: alu_out = b + (~a) + ~c_in;

or_ab: alu_out = {1’b0, a | b};

module t_Problem_5_27 ();

reg [7: 0] a, b;

reg c_in;

reg [2: 0] opcode;

reg [79: 0] ocs;

wire [8: 0] alu_out;

integer j, k;

Problem_5_27 M0 (alu_out, a, b, c_in, opcode);

initial #1000 $finish;

initial begin

#10 a = 8’h55; //0101_0101

b = 8’haa; //1010_1010

5: opcode = not_ab;

6: opcode = exor;

7: opcode = exnor;

endcase

end

always @(opcode)

Problem 5-28

// Eliminate feeedback from alu to Data_in

// Provide c_in to alu

Problem_5_27_ALU M0_ALU (alu_out, Data_Out_1, Data_Out_2, c_in, opcode);

Register_File M1_Reg_File (Data_Out_1, Data_Out_2, Data_in, Read_Addr_1,

Read_Addr_2, Write_Addr, Write_Enable, Clock);

endmodule

module Register_File (

// Test Plan: Register File

// Write to memory with walking ones

// Verify read of walking ones from each port

/*

module t_Register_File ();

wire [7: 0] Data_Out_1, Data_Out_2;

initial begin Clock = 0; forever #5 Clock = ~Clock; end

initial begin

Data_in = 8’b1000_0000;

Write_Enable = 1;

Write_Addr = 0;

Read_Addr_1 = 0;

Read_Addr_2 = 0;

input [7: 0] a, b,

input c_in,

input [2: 0] opcode

);

parameter [2: 0] add = 0;

parameter [2: 0] subtract = 1;

subtract_a: alu_out = b + (~a) + ~c_in;

or_ab: alu_out = {1’b0, a | b};

and_ab: alu_out = {1’b0, a & b};

not_ab: alu_out = {1’b0, (~a) &b};

exor: alu_out = {1’b0, a^b};

exnor: alu_out = {1’b0, a ~^ b};

endcase

endmodule

reg [2: 0] Read_Addr_1, Read_Addr_2, Write_Addr;

reg [2: 0] opcode;

reg Write_Enable, Clock;

reg c_in;

reg [79: 0] ocs;

integer k;

parameter [79: 0] ocs_0 = “add”;

parameter [79: 0] ocs_1 = “subtract”;

parameter [79: 0] ocs_2 = “subtract_a”;

parameter [79: 0] ocs_3 = “or_ab”;

parameter [79: 0] ocs_4 = “and_ab”;

parameter [79: 0] ocs_5 = “not_ab”;

parameter [79: 0] ocs_6 = “exor”;

parameter [79: 0] ocs_7 = “exnor”;

Problem_5_28 M0 (alu_out, Data_in, Read_Addr_1, Read_Addr_2, Write_Addr, opcode,

Write_Enable, c_in, Clock);

initial #500 $finish;

initial begin Clock = 0; forever #5 Clock = ~Clock; end

initial begin

else Data_in <= Data_in << 1;

Write_Addr <= Write_Addr + 1;

Read_Addr_1 <= Read_Addr_1 + 1;

Read_Addr_2 <= Read_Addr_2 + 1;

end

always @(opcode)

Problem 5-29

P3 <= Data

P2 <= P3

P1 <= P2

P0 <= P1

En

1

S_idle

{P3, P2, P1, P0}

<= {0,0,0,0}

Ld_regs

rst

module Datapath_Unit (

output reg[31:0] R0,

input [7:0] Data,

input Ld_regs, Ld_R0, clk, rst

module t_Datapath_Unit();

wire[31:0] R0;

wire [7:0] P0;

reg [7:0] Data;

reg Ld_regs, Ld_R0;

reg clk, rst;

Datapath_Unit M0(R0, Data, Ld_regs, Ld_R0, clk, rst);

initial #500 $finish;

initial begin clk = 0; forever #5 clk = ~clk; end

initial fork

#10 rst = 1;

#20 rst = 0;

#10 Data = 8’hfa;

#90 Data = 8’hbc;

join

endmodule

module Control_Unit (output reg Ld_regs, Ld_R0, input Ld, En, clk, rst);

parameter S_idle = 0, S_1 = 1, S_2=2, S_3 = 3, S_full = 4, S_wait = 5;

reg [2:0] state, next_state;

always @ (posedge clk, posedge rst)

if (rst) state <= S_idle;

else state <= next_state;

1; end

else next_state = S_idle; end

default next_state = S_idle;

endcase

end

endmodule

module test_Control_Unit ();

wire Ld_regs, Ld_R0;

reg Ld, En, clk, rst;

#130 Ld = 0;

#200 Ld = 1;

#210 Ld = 0;

join

endmodule

module Prob_5_29 (output [31:0] R0, input [7:0] Data, input En, Ld, clk, rst);

Control_Unit M0 (Ld_regs, Ld_R0, Ld, En, clk, rst);

Datapath_Unit M1 (R0, Data, Ld_regs, Ld_R0, clk, rst);

endmodule

initial #300 $finish;

initial begin clk = 0; forever #5 clk = ~clk; end

initial fork

En = 0;

Ld = 0;

#10 rst = 1;

#20 rst = 0;

module Prob_5_29 (output [31:0] R0, input [7:0] Data, input En, Ld, clk, rst);

Control_Unit M0 (Ld_regs, Ld_R0, Ld, En, clk, rst);

Datapath_Unit M1 (R0, Data, Ld_regs, Ld_R0, clk, rst);

endmodule

module test_Prob_5_29 ();

wire [31:0] R0;

reg [7:0] Data;

reg En, Ld, clk, rst;

#120 Ld = 1;

#130 Ld = 0;

#200 Ld = 1;

#210 Ld = 0;