Problem 5-13
module Universal_Shift_Reg (
output reg [3:0] Data_Out,
output MSB_Out, LSB_Out,
input [3:0] Data_In,
input MSB_In, LSB_In,
input s1, s0, clk, rst);
/*
Test Plan:
Verify initial reset
Verify idle
Verify shift right
Verify shift left
Universal_Shift_Reg M1 (Data_Out, MSB_Out, LSB_Out, Data_In, MSB_In, LSB_In, s1, s0, clk,
rst);
initial begin clk = 0; forever #5 clk = ~clk; end
initial #1000 $finish;
join
#120 fork
begin // Verify left shift
#10 Data_In = 4’b1111; s0 = 0; s1 = 0; LSB_In = 1; MSB_In = 1; end
#40 s1 = 1;
join
#250 fork
begin // Verify load
module Prob_5_14 (output P_odd, input D_in, clk, rst);
wire w1 = P_odd ^ D_in;
D_flop M0 (P_odd, w1, clk, rst);
endmodule
*/
module t_Prob_5_14 ();
wire P_odd;
reg D_in, clk, rst;
Prob_5_14 M0( P_odd, D_in, clk, rst);
initial #100 $finish;
Problem 5-15
module Problem_5_15 (
output reg [3: 0] count,
input [3: 0] initial_count,
input load, enable_b, clock, reset
);
module t_Problem_5_15 ();
wire [3: 0] count;
reg [3: 0] initial_count;
reg load, enable_b, clock, reset;
initial #500 $finish;
initial begin clock = 0; forever #5 clock = ~clock; end
initial fork
Problem 5-16
module Problem_5_16 (
output [7:0] count,
input [7:0] initial_count,
input load, enable_b, clock, reset
);
);
endmodule
module Problem_5_15_mod (
output reg [3: 0] count,
output RCO,
input [3: 0] initial_count,
input load, enable_b, clock, reset
module t_Problem_5_16 ();
wire [7: 0] count;
reg [7: 0] initial_count;
reg load, enable_b, clock, reset;
initial #500 $finish;
initial begin clock = 0; forever #5 clock = ~clock; end
initial fork
#15 initial_count = 8’b0000_0000;
#25 reset = 1;
#45 reset = 0;
join
initial fork
#55 enable_b = 0;
Problem 5-17
See the code table on p. 301.
module Johnson_Counter (
output reg [3: 0] count,
input enable,
input clock, reset
4’b1111,
4’b1110,
4’b1100,
4’b1000: count <= {count[2: 0], 1’b0};
default: count <= 0;
endcase
endmodule
module t_Johnson_Counter ();
wire [3: 0] count;
#400 enable = 1;
join
endmodule
Problem 5-18
// Assumption: positive-edge sensitive, active-high reset.
// Assumption: count from reset value
module BCD_Counter (
module t_BCD_Counter ();
wire [3: 0] count;
reg clk, rst;
BCD_Counter M0 (count, clk, rst);
initial #200 $finish;
initial begin
Problem 5-19
// Assumption: positive-edge sensitive, active-high reset.
// Assumption: count from reset value
module t_Modulo_6_Counter ();
wire [2: 0] count;
reg clk, rst;
Modulo_6_Counter M0 (count, clk, rst);
Problem 5-20
module Problem_5_20 (
output reg [15: 0] R0,
input [7:0] Data,
input Clr_P1_P0, Ld_P1_P0, Ld_R0, clock, rst
);
// Test Plan
// verify power-up reset
// Verify pipeline action
// Verify load of R0 action
initial fork
Data = 8’haa;
#10 rst = 0; // Power-up reset
#20 rst = 1;
#50 rst = 0;
#20 Ld_P1_P0 = 0;
Problem 5-21
module Prob_5_21 #(parameter word_size = 8)(
output reg [word_size-1: 0] count,
input enable, clock, reset
);
initial #500 $finish;
initial begin clock = 0; forever #5 clock = ~clock; end
initial fork
#20 reset = 1;
#30 reset = 0;
Problem 5-22
module Prob_5_22 (
output reg [2: 0] count,
input [2: 0] data_in,
input [1: 0] up_dwn,
input load, clk, rst_bar);
Test plan to test the following features:
• Count upwards and repeat the count
module t_Prob_5_22 ();
wire [2: 0] count,
reg [2: 0] data_in,
reg [1: 0] up_dwn,
reg load, clk, rst_bar;
#350 up_dwn = 2; // count down
#570 up_dwn = 0;
Problem 5-23
module Problem_5_23 (
// 8-bit ring counter, MSB to LSB
// Assume positive-edge sensitive; active high reset
#( parameter size = 8)(
output reg [size -1: 0] count,
input clk, rst
);
Problem_5_23 M0 (count, clk, rst);
initial #500 $finish;
initial begin clk = 0; forever #5 clk = ~clk; end
initial fork
Problem 5-24
module Problem_5_24a (count, clk, reset);
output reg [7:0] count,
input clk, reset;
always @ (state) begin
next_state = 1; count = 1;
case (state)
0: begin next_state = 1; count = 1; end
1: begin next_state = 2; count = 2; end
2: begin next_state = 3; count = 1; end
3: begin next_state = 4; count = 4; end
module t_Problem_5_24a ();
wire [7:0] count;
reg clk, reset;
Problem_5_24a M0(count, clk, reset);
