Problem 3-1
Problem 3-2
Par_Detect ParityBit_in
clk rst
Assumption: asynchronous reset
rst
Problem 3-3
q2 q1 q0 q2+ q1+ q0+
s0 0 0 0 0 1 0
s2 0 1 0 1 0 0
s4 1 0 0 1 1 0
s6 1 1 0 0 0 0
Problem 3-4
1/1
State transition graph – Mealy Machine
reset
Problem 3 – 5
Problem 3-6
No static-0 or static-1 hazards.
Problem 3-7
reset
B_in = 0
B_in = 1
Problem 3-8
Tie the machines together to complete the solution:
0
s_0
rst
0
s_1
1,x
0,x
0,x
1,x
0,x
bit, done
Control
Unit Counter
incr
done
incr is asserted as the output of the FSM n
Assumption: asynchronous reset. Bit_in clocked on rising edge.
MSB (0) of 0111 arrives first. Transitions for reset condition are omitted for simplicity.
rst 01s0
0
s1
0
s2
0
s3
0
s4
1
11
1
0
Bit_in
Problem 3-9
);
parameter s0 = 0;
parameter s1 = 1;
reg state, next_state;
always @ (negedge clk, posedge rst)
if first == 1) state <= s0;
else state <= next_state;
initial #400 $finish;
initial begin
rst = 0;
#10 rst = 1;
#20 rst = 0;
#147 rst = 1; // reset on-the-fly
#5 rst = 0;
end
Problem 3-10
NRZI Line encoder
Problem 3-11
Problem 3-12
Problem 3-13