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Multiple parallel pipelines are used in __________ .
A. speculative execution
B. data flow analysis
C. superscalar execution
D. branch prediction
The _________ contains a word of data to be written to memory or the word most
recently read.
A. MAR
B. PC
C. MBR
D. IR
___________ states that performance increase is roughly proportional to square root of
increase in complexity.
A. Pollack's Rule
B. Moore's Law
C. Amdahl's Law
D. MOESI Rule
The ________ introduced a full-blown superscalar design with out-of-order execution.
A. Pentium
B. Pentium Pro
C. 386
D. 486
The groupings of micro-operations must follow which rule?
A. a sequence of events does not need to be followed
B. use read to and write from the same register in one time unit
C. conflicts must be avoided
D. all of the above
The _________ table provides the value of the next output when the inputs and the
present output are known, which is exactly the information needed to design the counter
or any sequential circuit.
A. excitation
B. Kenough
C. J-K flip-flop
D. FPGA
_______ instructions are needed to transfer programs and data into memory and the
results of computations back out to the user.
A. I/O
B. Transfer
C. Control
D. Branch
For random-access memory, __________ is the time from the instant that an address is
presented to the memory to the instant that data have been stored or made available for
use.
A. memory cycle time
B. direct access
C. transfer rate
D. access time
The ________ scheduler is also known as the dispatcher.
A. long-term
B. medium-term
C. short-term
D. I/O
Binary addition is exactly the same as Boolean algebra.
_________ is a principle by which two variables are independent of each other.
A. Opcode
B. Orthogonality
C. Completeness
D. Autoindexing
An I/O device is referred to as a __________.
A. CPU
B. control device
C. peripheral
D. register
The ________ feature enables moving dirty data from one CPU to another without
writing to L2 and reading the data back in from external memory.
A. migratory lines
B. DDI
C. VFP unit
D. IPIs
It is a(n) _________ issue whether the multiply instruction will be implemented by a
special multiply unit or by a mechanism that makes repeated use of the add unit of the
system.
A. architectural
B. memory
C. mechanical
D. organizational
________ is implemented with combinational circuits.
A. Nano memory
B. Random access memory
C. Read only memory
D. No memory
The ________ gives a program access to the hardware resources and services available
in a system through the user instruction set architecture supplemented with high-level
language library calls.
A. JCL
B. ISA
C. ABI
D. API
__________ is a design principle employed in designing the PDP-10 instruction set.
A. Orthogonality
B. Completeness
C. Direct addressing
D. All of the above
Which of the following is an Intel 8085 external signal?
A. CLK(OUT)
B. read control
C. HOLDA
D. all of the above
One increment, or pulse, of a clock is referred to as a __________ .
A. clock cycle
B. clock rate
C. clock speed
D. cycle time
GPGPU is a computing platform and programming model created by NVIDIA.
When a microinstruction is read from the control memory it is transferred to a
_________.
A. control buffer register
B. control memory
C. control address register
D. control unit
With respect to changes in values, the __________ Mean gives equal weight to all of
the values in the data set.
A. Harmonic
B. Arithmetic
C. Composite
D. Geometric
Greater ability to withstand shock and damage, improvement in the uniformity of the
magnet film surface to increase disk reliability, and a significant reduction in overall
surface defects to help reduce read-write errors, are all benefits of ___________.
A. magnetic read and write mechanisms
B. platters
C. the glass substrate
D. a solid state drive
The Thunderbolt protocol _________ layer is responsible for link maintenance
including hot-plug detection and data encoding to provide highly efficient data transfer.
A. cable
B. application
C. common transport
D. physical
________ refers to the process of initiating instruction execution in the processor's
functional units.
A. Instruction issue
B. In-order issue
C. Out-of-order issue
D. Procedural issue
The disadvantage of _________ is that the amount of data that can be stored on the long
outer tracks is only the same as what can be stored on the short inner tracks.
A. SSD
B. CAV
C. ROM
D. CLV
The _________ contains logic for performing a communication function between the
peripheral and the bus.
A. I/O channel
B. I/O module
C. I/O processor
D. I/O command
In a _________, binary values are stored using traditional flip-flop logic-gate
configurations.
A. ROM
B. SRAM
C. DRAM
D. RAM
The entire set of parameters, including return address, which is stored for a procedure
invocation is referred to as a _________.
A. branch
B. stack frame
C. pop
D. push
The _________ stage includes ALU operations, cache access, and register update.
A. decode
B. execute
C. fetch
D. write back
Both clusters and symmetric multiprocessors provide a configuration with multiple
processors to support high-demand applications.
_________ is a random access type of memory that enables one to make a comparison
of desired bit locations within a word for a specified match, and to do this for all words
simultaneously, thus retrieving a word based on a portion of its contents rather than its
address.
In a _________ interface there are multiple lines connecting the I/O module and the
peripheral and multiple bits are transferred simultaneously.
Intel's ________ technology is a set of highly optimized instructions for multimedia
tasks.
A typical computer system is equipped with a hierarchy of memory subsystems, some
internal to the system and some external.
Not common on contemporary architectures, ___________ requires only one memory
reference and no special calculation, but provides only a limited address space.
The ________ rate is the rate at which data can be transferred into or out of a memory
unit.
With __________ the processor looks ahead in the instruction code fetched from
memory and predicts which branches, or groups of instructions, are likely to be
processed next.
The categories for the major functions or requirements for an I/O module are: control
and timing, device communication, data buffering, error detection, and _________.
_________ processors, with their simpler instruction format, typically use hardwired
control units.
The __________ register contains the value to be stored in memory or the last value
read from memory.
Instruction-level parallelism is also determined by __________, which is the time until
the result of an instruction is available for use as an operand in a subsequent instruction.
The most important general categories of data are: addresses, numbers, characters, and
_________.
________ threading is when many similar or identical tasks are spread across multiple
processors.
It has become common practice to use a symbolic representation of machine
instructions.
Because the 82C55A is programmable via the control register, it can be used to control
a variety of simple peripheral devices.
Memory references are faster than register references.
Extending the range of numbers that can be expressed by increasing the bit length is
referred to as __________.
__________ is a way of increasing the efficiency of the pipeline by making use of a
branch that does not take effect until after execution of the following instruction.
