CS 92761

subject Type Homework Help
subject Pages 22
subject Words 2132
subject Authors William Stallings

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page-pf1
The number of bits used to represent various data types is an example of an
architectural attribute.
GPUs can be found in almost all of today's workstations, laptops, tablets, and
smartphones.
During a read or write operation, the head rotates while the platter beneath it stays
stationary.
The memory transfer rate has not kept up with increases in processor speed.
page-pf2
Raw speed is far more important than how a processor performs when executing a
given application.
Both sequential access and direct access involve a shared read- write mechanism.
Instruction pipelining is a powerful technique for enhancing performance but requires
careful design to achieve optimum results with reasonable complexity.
page-pf3
It is not necessary for the ALU to signal when overflow occurs.
Changes in computer technology are finally slowing down.
The base with index and displacement mode sums the contents of the base register, the
index register, and a displacement to form the effective address.
Each phase of the instruction cycle can be decomposed into a sequence of elementary
micro-operations.
page-pf4
The method of using the same lines for multiple purposes is known as time
multiplexing.
Both sign-magnitude representation and twos complement representation use the most
significant bit as a sign bit.
A set of I/O modules is a key element of a computer system.
The superscalar approach has now become the standard method for implementing
page-pf5
high-performance microprocessors.
Privileged instructions are certain instructions that are designated special and can be
executed only by the monitor.
A removable disk can be removed and replaced with another disk.
Within the processor there is a set of registers that function as a level of memory above
main memory and cache in the hierarchy.
page-pf6
In a volatile memory, information decays naturally or is lost when electrical power is
switched off.
The x86 includes hardware for both segmentation and paging.
Secondary memory is used to store program and data files and is usually visible to the
programmer only in terms of individual bytes or words.
RAID is a set of physical disk drives viewed by the operating system as a single logical
page-pf7
drive.
One technique for implementing a control unit is referred to as hardwired
implementation, in which the control unit is essentially a state machine circuit.
The disadvantage of immediate addressing is that the size of the number is restricted to
the size of the address field.
Workstation systems cannot support highly sophisticated engineering and scientific
applications.
page-pf8
The simplest instruction issue policy is to issue instructions in the exact order that
would be achieved by sequential execution (in-order issue) and to write results in that
same order (in-order completion).
The raw speed of the microprocessor will not achieve its potential unless it is fed a
constant stream of work to do in the form of computer instructions.
SSD performance has a tendency to speed up as the device is used.
page-pf9
For addresses that reference memory the range of addresses that can be referenced is
not related to the number of address bits.
The unit of transfer must equal a word or an addressable unit.
Changes in technology not only influence organization but also result in the
introduction of more powerful and more complex architectures.
A bit near the center of a rotating disk travels past a fixed point slower than a bit on the
outside.
page-pfa
Utilizing a branch target buffer (BTB), the _________ uses a dynamic branch
prediction strategy based on the history of recent executions of branch instructions.
A. 486
B. Pentium
C. Intel Core
D. Pentium Pro
Addresses are a form of data.
_________ instructions provide computational capabilities for processing number data.
A. Boolean
B. Logic
C. Memory
page-pfb
D. Arithmetic
The _________ instruction includes an implied address.
A. skip
B. rotate
C. stack
D. push
With _______, register banks are replicated so that multiple threads can share the use of
pipeline resources.
A. SMT
B. pipelining
C. scalar
D. superscalar
page-pfc
The x86 data type that is a signed binary value contained in a byte, word, or
doubleword, using twos complement representation is _________.
A. general
B. ordinal
C. integer
D. packed BCD
The Patterson study examined the dynamic behavior of _________ programs,
independent of the underlying architecture.
A. HLL
B. RISC
C. CISC
D. all of the above
page-pfd
Which digit represents "hundreds" in the number 8732?
A. 8
B. 7
C. 3
D. 2
The interconnection structure must support which transfer?
A. memory to processor
B. processor to memory
C. I/O to or from memory
D. all of the above
The only form of addressing for branch instructions is _________ addressing.
A. register
B. relative
C. base
page-pfe
D. immediate
Counters can be designated as _________.
A. asynchronous
B. synchronous
C. both asynchronous and synchronous
D. neither asynchronous or synchronous
Instead of the first instruction producing a value that the second instruction uses, with
___________ the second instruction destroys a value that the first instruction uses.
A. in-order issue
B. resource conflict
C. antidependency
D. out-of-order completion
page-pff
The binary string 110111100001 is equivalent to __________.
A. DE116
B. C7816
C. FF6416
D. B8F16
_________ determines the control and pipeline organization.
A. Calculation
B. Execution sequencing
C. Operations performed
D. Operands used
page-pf10
The 8237 DMA is known as a _________ DMA controller.
A. command
B. cycle stealing
C. interrupt
D. fly-by
A __________ is a core designed to perform parallel operations on graphics data.
A. MIC
B. ALU
C. GPU
D. PGD
________ increases the prefetch buffer size to 8 bits.
A. CDRAM
B. RDRAM
C. DDR3
page-pf11
D. all of the above
The ________ controls the movement of data and instructions into and out of the
processor.
A. control unit
B. ALU
C. shifter
D. branch
________ provides service to customers in the form of software, specifically
application software, running on and accessible in the cloud.
A. PaaS
B. CaaS
C. SaaS
D. IaaS
page-pf12
An I/O module that takes on most of the detailed processing burden, presenting a
high-level interface to the processor, is usually referred to as an _________.
A. I/O channel
B. I/O command
C. I/O controller
D. device controller
A common example of system interconnection is by means of a __________.
A. register
B. system bus
C. data transport
D. control device
page-pf13
CPUs make use of _________ counters, in which all of the flip-flops of the counter
change at the same time.
A. synchronous
B. asynchronous
C. clocked S-R
D. timed ripple
Architectural attributes include __________ .
A. I/O mechanisms
B. control signals
C. interfaces
D. memory technology used
________ is when the result may be larger than can be held in the word size being used.
A. Overflow
B. Arithmetic shift
page-pf14
C. Underflow
D. Partial product
__________ representation is almost universally used as the processor representation
for integers.
A. Biased
B. Twos compliment
C. Sign-magnitude
D. Decimal
In ________ representation the rule for forming the negation of an integer is to invert
the sign bit.
A. ones complement
B. twos complement
C. biased
D. sign-magnitude
page-pf15
With __________ the data transfer is synchronized to both the rising and falling edge of
the clock, rather than just the rising edge.
A. CDRAM
B. SDRAM
C. DDR-DRAM
D. RDRAM
__________ is a good candidate to replace or supplement DRAM for main memory.
A. STT-RAM
B. ReRAM
C. RamBus
D. PCRAM
page-pf16
A(n) _________ is generated by some condition that occurs as a result of an instruction
execution.
A. timer interrupt
B. I/O interrupt
C. program interrupt
D. hardware failure interrupt
The cache holds recently accessed data.
___________ potentially increases the amount of work available for the processor to
execute.
A. Branch prediction
B. Performance balance
C. Pipelining
D. BIPS
page-pf17
The EU can issue up to ________ different instructions simultaneously from different
threads.
A. four
B. five
C. six
D. seven
The ________ determines the opcode and the operand specifiers.
A. decode instruction
B. fetch operands
C. calculate operands
D. execute instruction
page-pf18
With no multithreading, _________ is the simple pipeline found in traditional RISC and
CISC machines.
A. superscalar
B. single-threaded scalar
C. blocked multithreaded scalar
D. interleaved multithreaded scalar
__________ enables the processor to keep its execution engines as busy as possible by
executing instructions that are likely to be needed.
The rightmost digit is called the _________ digit.
page-pf19
The major components of the processor are an arithmetic and logic unit (ALU) and a
__________.
Today the most commonly used character code is the IRA, referred to in the United
States as _____________.
The register file employs much shorter addresses than addresses for cache and memory.
It is common for programs, both system and application, to continue to exhibit new
bugs after years of operation.
page-pf1a
To convert a number from binary notation to decimal notation all that is required is to
multiply each binary digit by the appropriate power of ________ and add the results.
A ________ architecture replicates each of the pipeline stages so that two or more
instructions at the same stage of the pipeline can be processed simultaneously.
The instruction set is the programmer's means of controlling the processor.
page-pf1b
The typical recording technique used in serial tapes is referred to as _________
recording.
The delay by the propagation time of signals through the gate is known as the gate
delay.
The acronym CISC stands for _________.
It is more difficult to write a firmware program than a software program.
page-pf1c
_________ is the easiest multithreading approach to implement.
A __________ control unit operates by executing microinstructions that define the
functionality of the control unit.
The _________ scheduler breaks up each thread block it is processing into warps.

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