The MIPS R4000 processor chip is partitioned into two sections, one containing the
CPU and the other containing a _________ for memory management.
In a __________ number system, each number is represented by a string of digits in
which each digit position i has an associated weight ri, where r is the radix of the
number system.
The cache is capable of handling global as well as local variables.
The most common classes of interrupts are: program, timer, I/O and ________.
The main drawback of the bus organization is reliability.
Although convenient for computers, the binary system is exceedingly cumbersome for
human beings.
__________ is when the control unit examines the opcode and generates a sequence of
micro-operations based on the value of the opcode.
An alternative, which has been used in many CISC processors, is to implement a
__________ control unit.
The control unit design is very flexible.
A __________ is a communication pathway connecting two or more devices.
A _________ system groups the user’s program with programs for other users and is
submitted by a computer operator, with results being printed out for the user upon
completion of the program.
The register file is on the same chip as the ALU and control unit.
Logical functions are implemented by the interconnection of decoders.
External, nonvolatile memory is referred to as ___________ or auxiliary memory.
_________ instructions are those that can be executed only while the processor is in a
certain privileged state or is executing a program in a special privileged area of
memory.
The instruction set, the number of bits used to represent various data types, I/O
mechanisms and techniques for addressing memory are all examples of _________
attributes.
The Fermi architecture upgraded from the IEEE 754-1985 floating-point arithmetic
standard to the IEEE 754-2008 standard.
The PDP-11 is the first member of the LSI-11 family that was offered as a single board
processor.