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With _________ encoding one field is used to determine the interpretation of another
field.
A. resource
B. indirect
C. direct
D. functional
Which of the following is a hardware technique that can be used in a superscalar
processor to enhance performance?
A. duplication of resources
B. out-of-order issue
C. renaming
D. all of the above
The _________ defines the repertoire of machine language instructions that a computer
can follow.
A. ABI
B. API
C. HLL
D. ISA
The data lines provide a path for moving data among system modules and are
collectively called the _________.
A. control bus
B. address bus
C. data bus
D. system bus
When using the __________ technique all write operations made to main memory are
made to the cache as well.
A. write back
B. LRU
C. write through
D. unified cache
The _________ scheduler determines which programs are admitted to the system for
processing.
A. long-term
B. medium-term
C. short-term
D. I/O
A _________ is a high-definition video disk that can store 25 Gbytes on a single layer
on a single side.
A. DVD
B. DVD-R
C. DVD-RW
D. Blu-ray DVD
The _________ is a 32-bit ALU with 64 registers that can be configured to operate as
four 8-bit ALUs, two 16-bit ALUs, or a single 32-bit ALU.
A. PDP-11
B. 8832
C. 3033
D. 8818
________ is used for debugging.
A. Direction flag
B. Alignment check
C. Trap flag
D. Identification flag
Four bits is called a _________.
A. radix point
B. byte
C. nibble
D. binary digit
The superscalar approach can be used on __________ architecture.
A. RISC
B. CISC
C. neither RISC nor CISC
D. both RISC and CISC
A _________ is a mechanism that provides for communication among CPU,
main memory, and I/O.
A. system interconnection
B. CPU interconnection
C. peripheral
D. processor
An increase in clock rate means that individual operations are executed _____.
A. the same
B. slower
C. with very little change
D. more rapidly
Each instruction executed during an instruction cycle is made up of shorter ______.
A. executions
B. subcycles
C. steps
D. none of the above
The set of microinstructions is stored in the __________.
A. control address register
B. control buffer register
C. control memory
D. control word
Virtual memory schemes make use of a special cache called a ________ for page table
entries.
A. TLB
B. HLL
C. VMC
D. SPB
individual blocks or records have a unique address based on physical location with
__________.
A. associative access
B. physical access
C. direct access
D. sequential access
__________ is when a positive exponent exceeds the maximum possible exponent
value.
A. Significand underflow
B. Significand overflow
C. Exponent overflow
D. Exponent underflow
The ________ specifies the operation to be performed.
A. source operand reference
B. opcode
C. next instruction reference
D. processor register
A loop that iterates over an array of data can be split up into a number of smaller
parallel loops in individual threads that can be scheduled in parallel when using
________ threading.
A. multi-process
B. fine-grained
C. hybrid
D. coarse
_________ attributes include hardware details transparent to the programmer.
A. Interface
B. Organizational
C. Memory
D. Architectural
The ________ is responsible for maintaining coherency among L1 data caches.
A. VFP unit
B. distributed interrupt controller
C. snoop control unit (SCU)
D. watchdog
The interface between processor and ___________ is the most crucial pathway in the
entire computer because it is responsible for carrying a constant flow of program
instructions and data between memory chips and the processor.
A. main memory
B. pipeline
C. clock speed
D. control unit
The _________ was designed to provide a powerful and flexible instruction set within
the constraints of a 16-bit minicomputer.
A. PDP-1
B. PDP-8
C. PDP-11
D. PDP-10
The set of all the tracks in the same relative position on the platter is referred to as a
_________.
A. floppy disk
B. single-sided disk
C. sector
D. cylinder
A _________ is an actual location in main memory.
A. logical address
B. partition address
C. base address
D. physical address
The R4000 pipeline stage where the instruction result is written back to the register file
is the __________ stage.
A. write back
B. tag check
C. data cache
D. instruction execute
The parallel code in the form of a function to be run on GPU is the ________ .
A. grid
B. thread
C. kernel
D. none of the above
It is a(n) _________ design issue whether a computer will have a multiply instruction.
A. architectural
B. memory
C. elementary
D. organizational
Moving the sign bit to the new leftmost position and filling in with copies of the sign bit
is called _________.
A. sign extension
B. range extension
C. bit extension
D. partial extension
When large volumes of data are to be moved, a more efficient technique is direct
memory access (DMA).
The instruction location immediately following the delayed branch is referred to as the
________.
A. delay load
B. delay file
C. delay slot
D. delay register
The desktop application(s) that require the great power of today's microprocessor-based
systems include___________.
A. image processing
B. speech recognition
C. videoconferencing
D. all of the above
With _________ the virtual address is the same as the physical address.
A. unsegmented unpaged memory
B. unsegmented paged memory
C. segmented unpaged memory
D. segmented paged memory
Committing or _________ the instruction is when instructions are conceptually put
back into sequential order and their results are recorded.
The decimal system has a radix of _________.
A __________ program can be divided into three general sections: code to be run on the
device, code to be run on the host, and the code related to the transfer of data between
the host and the device.
A single piece of silicon is called a ________.
RAID levels 2 and 3 make use of a _________ access technique in which all member
disks participate in the execution of every I/O request.
___________ is the ability to issue more than one instruction in every processor clock
cycle.
The number of blocks per kernel launch is called a __________ .
The four principal approaches to multithreading are: interleaved (fine-grained), blocked
(coarse-grained), simultaneous, and ________.
A combinational circuit consists of n binary inputs and m binary outputs.
In the operation of the Intel Core each instruction is translated into one or more
fixed-length RISC instructions known as _________.
An I/O channel has the ability to execute I/O instructions, which gives it complete
control over I/O operations.
The collection of different instructions that the processor can execute is referred to as
the processor's _________.
The __________ instruction set is designed to increase the performance of ARM
implementations that use a 16-bit or narrower memory data bus and to allow better code
density than provided by the ARM instruction set.
A ________ machine is an instance of an operating system along with one or more
applications running in an isolated memory partition within the computer, enabling
different operating systems to run in the same computer at the same time, as well as
preventing applications from interfering with each other.
All DRAMs require a refresh operation.
Each gate is defined in three ways: graphic symbol, algebraic notation, and
__________.
__________ registers are used by the control unit to control the operation of the
processor and by privileged operating system programs to control the execution of
programs.
