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It is not possible to connect I/O controllers directly onto the system bus.
The execute cycle is simple and predictable.
The basic element of a semiconductor memory is the memory cell.
The cycle time of an instruction pipeline is the time needed to advance a set of
instructions one stage through the pipeline.
The superscalar approach depends on the ability to execute multiple instructions in
parallel.
For each 1 on the multiplier, an add and a shift operation are required; but for each 0
only a shift is required.
The generic timer handles interrupt detection and interrupt prioritization.
Both the structure and functioning of a computer are, in essence, simple.
Booth's algorithm performs more additions and subtractions than a
straightforward algorithm.
Cloud service providers use massive high-performance banks of servers to satisfy
high-volume, high-transaction-rate applications for a broad spectrum of clients.
RAM must be provided with a constant power supply.
A control hazard occurs when two or more instructions that are already in the pipeline
need the same resource.
The SSDs now on the market use a type of semiconductor memory referred to as flash
memory.
Microprogramming eases the task of designing and implementing the control unit and
provides support for the family concept.
The use of common data paths simplifies the interconnection layout and the control of
the processor.
The hierarchical nature of complex systems is essential to both their design and their
description.
In a system without virtual memory, the effective address is a virtual address or a
register.
The numbers represented in floating-point notation are not spaced evenly along the
number line, as are fixed-point numbers.
A static RAM will hold its data as long as power is supplied to it.
Three of the most common uses of stack addressing are relative addressing,
base-register addressing, and indexing.
The x86 is equipped with a variety of addressing modes intended to allow the efficient
execution of high-level languages.
With direct addressing, the length of the address field is usually less than the word
length, thus limiting the address range.
An interrupt is generated from software and it is provoked by the execution of an
instruction.
The most important system program is the OS.
Semiconductor memory comes in packaged chips.
An error-correcting code enhances the reliability of the memory at the cost of added
complexity.
At the completion of the execute cycle a test is made to determine whether any enabled
interrupts have occurred, and if they have, the interrupt cycle occurs.
In general, the more devices attached to the bus, the greater the bus length and hence
the greater the propagation delay.
The execution of a program consists of the sequential execution of instructions.
In-order completion requires more complex instruction issue logic than out-of-order
completion.
Flash memory is only used for internal memory applications.
With superscalar organization increased performance can be achieved by increasing the
number of parallel pipelines.
Both the structure and functioning of a computer are, in essence,simple.
Register renaming eliminates antidependencies and output dependencies.
Designers wrestle with the challenge of balancing processor performance with that of
main memory and other computer components.
A computer organization does not need to be designed to implement a particular
architectural specification.
A number of chips can be grouped together to form a memory bank.
With write back updates are made only in the cache.
Because all devices on a synchronous bus are tied to a fixed clock rate, the system
cannot take advantage of advances in device performance.
A tactic similar to the delayed branch is the _________, which can be used on LOAD
instructions.
A. delayed load
B. delayed program
C. delayed slot
D. delayed register
The _________ allows multiple levels of nested calls or interrupts and it can be used to
support branching and looping.
A. stack
B. register
C. counter
D. firmware
The _________ contains the address of an instruction to be fetched.
A. instruction register
B. memory address register
C. memory buffer register
D. program counter
A single micro-operation generally involves which of the following?
A. a transfer between registers
B. a transfer between a register and an external bus
C. a transfer between a register and the ALU
D. all of the above
Virtually all contemporary computer designs are based on concepts developed by
__________ at the Institute for Advanced Studies, Princeton.
A. John Maulchy
B. John von Neumann
C. Herman Hollerith
D. John Eckert
_________ is where individual instructions are executed through a pipeline of stages so
that while one instruction is executing in one stage of the pipeline, another instruction is
executing in another stage of the pipeline.
A. Superscalar
B. Scalar
C. Pipelining
D. Simultaneous multithreading
The _________ holds the last instruction fetched.
A. PC
B. MBR
C. MAR
D. IR
__________ are bits set by the processor hardware as the result of operations.
A. MIPS
B. Condition codes
C. Stacks
D. PSWs
Which of the following is a functionally complete set?
A. AND, NOT
B. NOR
C. AND, OR, NOT
D. all of the above
The control unit (CU) does the actual computation or processing of data.
The most common scheme in implementing the integer portion of the ALU is:
A. sign-magnitude representation
B. biased representation
C. twos complement representation
D. ones complement representation
________ registers may be used only to hold data and cannot be employed in the
calculation of an operand address.
A. General purpose
B. Data
C. Address
D. Condition code
Which of the following is a control unit input?
A. IR
B. ALU flags
C. clock
D. all of the above
A group of threads assigned to a particular SM is a __________ .
A. block
B. grid
C. unit
D. kernel
A _________ problem arises when multiple copies of the same data can exist in
different caches simultaneously, and if processors are allowed to update their own
copies freely, an inconsistent view of memory can result.
A. cache coherence
B. cluster
C. failover
D. failback
__________ are the functional, or atomic, operations of a processor.
A. Micro-operations
B. Interrupts
C. Subcycles
D. All of the above
_________ are included in IEEE 754 to handle cases of exponent underflow.
A. Subnormal numbers
B. Guard bits
C. Normal numbers
D. Radix points
The best known of the SPEC benchmark suites is __________ .
A. SPEC CPU2006
B. SPECjvm2008
C. SPECsfs2008
D. SPEC SC2013
_________ is a subfield that is used to indicate a conditional branch.
A. ZERION
B. S2-S0
C. SELDR
D. OSEL
A _________ is a bundle of 32 threads that start at the same starting address and their
thread IDs are consecutive.
A. warp
B. grid
C. block
D. grouping
The Intel Core i7-990X chip supports _________ forms of external communications to
other chips.
A. 4
B. 2
C. 6
D. 8
The __________ module handles multiple levels of interrupt signals.
A. interrupt control
B. incrementer address latch
C. serial I/O control
D. decrementer address latch
The ARM architecture supports _______ execution modes.
A. 2
B. 8
C. 11
D. 7
The ________ flip-flop has two inputs and all possible combinations of input values are
valid.
A. J-K
B. D
C. S-R
D. clocked S-R
A ________ instruction can be used to account for data and branch delays.
A. SUB
B. NOOP
C. JUMP
D. all of the above
__________ increases the data transfer rate by increasing the operational frequency of
the RAM chip and by increasing the prefetch buffer from 2 bits to 4 bits per chip.
A. DDR2
B. RDRAM
C. CDRAM
D. DDR3
In the number 472.156 the 2 is the _________.
A. most significant digit
B. radix point
C. least significant digit
D. none of the above
The __________ measures the ability of a computer to complete a single task.
A. clock speed
B. speed metric
C. execute cycle
D. cycle time
In reference to access time to a two-level memory, a _________ occurs if an accessed
word is not found in the faster memory.
A. miss
B. hit
C. line
D. tag
For _________, the address field references a main memory address and the referenced
register contains a positive displacement from that address.
A. indexing
B. base-register addressing
C. relative addressing
D. all of the above
Data are transferred to and from the disk in __________.
A. tracks
B. gaps
C. sectors
D. pits
__________ has the advantage of flexibility, but the disadvantage of complexity.
A. Stack addressing
B. Displacement addressing
C. Direct addressing
D. Register addressing
The _________ function is needed to ensure that a sending QPI entity does not
overwhelm a receiving QPI entity by sending data faster than the receiver can process
the data and clear buffers for more incoming data.
__________ means that the number is too small to be represented and it may be
reported as 0.
A. Negative underflow
B. Exponent underflow
C. Positive underflow
D. Significand underflow
We can broadly classify external devices into three categories: human readable,
communication, and __________.
Many processor designs include a register or set of registers often known as the
_________ that contain status information and condition codes.
RAM, ROM, PROM, EPROM, EEPROM, and flash memory are all examples of
__________ memory types.
The number of machine cycles for an instruction depends on the number of times the
processor must communicate with internal devices.
The digital circuitry in digital computers and other digital systems is designed, and its
behavior is analyzed, with the use of a mathematical discipline known as __________.
_________ is a measure of the ability of the processor to take advantage of
instruction-level parallelism.
The __________ generated by a microinstruction are used to cause register transfers
and ALU operations.
The simplest of the error-correcting codes is the _________ code.
The time required to move the disk arm to the required track is the __________.
_______ is an animation engine used by Valve for its games and licensed for other
game developers.
Software cache coherence schemes attempt to avoid the need for additional hardware
circuitry and logic by relying on the compiler and operating system to deal with the
problem.
RISC processors are more responsive to interrupts because interrupts are checked
between rather elementary operations.
A ________ controls multiple high-speed devices and, at any one time, is dedicated to
the transfer of data with one of those devices.
An approach where all processors have access to all parts of main memory using loads
and stores, with the memory access time of a processor differing depending on which
region of main memory is accessed, is _________.
The _________ GPU has a total of 16 SMs x 32 CUDA cores/SM, or 512 CUDA cores.
Superscalar instruction issue policies are grouped into the following categories: in-order
issue with in-order completion, out-of-order issue with out-of-order completion, and
____________.
__________ format is a fully specified, fixed-length binary encoding that allows data
interchange between different platforms and that can be used for storage.
