CMCS 63257

subject Type Homework Help
subject Pages 18
subject Words 1728
subject Authors William Stallings

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page-pf1
Swapping is an I/O operation.
The sequence of instruction cycles are always the same as the written sequence of
instructions that make up the program.
The value of the mode field determines which addressing mode is to be used.
The predict-never-taken approach is the most popular of all the branch prediction
methods.
page-pf2
Addition and subtraction can be performed on numbers in twos
complement notation by treating them as unsigned integers.
The ABI is the boundary between hardware and software.
It is possible to improve pipeline performance by automatically rearranging instructions
within a program so that branch instructions occur later than actually desired.
page-pf3
The transfer time to or from the disk does not depend on the rotation speed of the disk.
Compared with addition and subtraction, multiplication is a complex operation, whether
performed in hardware of software.
A particular architecture may span many years and encompass anumber of different
computer models, its organization changing with changing technology.
The Cortex-A8 targets a wide variety of mobile and consumer applications including
mobile phones, set-top boxes, gaming consoles and automotives
navigation/entertainment systems.
page-pf4
With a fixed-point notation it is possible to represent a range of positive and negative
integers centered on or near 0.
Each micro-operation of the fetch cycle involves the movement of data into or out of a
register.
DRAM is much costlier than SRAM.
page-pf5
Actual floating-point representations include a special bit pattern to designate zero.
Overflow is a less serious problem because the result can generally be satisfactorily
approximated by 0.
The OS must determine how much processor time is to be devoted to the execution of a
particular user program.
Knowing the machine instruction set does not play a part in knowing the functions that
the processor must perform.
page-pf6
Hardware-based solutions are generally referred to as cache coherence _______.
A. clusters
B. streams
C. protocols
D. vectors
The situation where the second instruction needs data produced by the first instruction
to execute is referred to as __________.
A. true data dependency
B. output dependency
C. procedural dependency
D. antidependency
page-pf7
________ is a protocol used to issue instructions.
A. Micro-ops
B. Scalar
C. SIMD
D. Instruction issue policy
The _________ performs transcendental operations, such as cosine, sine, reciprocal,
and square root, in a single clock cycle.
A. SM
B. SIMD
C. SFU
D. FMA
__________ can be caused by harsh environmental abuse, manufacturing defects, and
wear.
A. SEC errors
B. Hard errors
page-pf8
C. Syndrome errors
D. Soft errors
Positive numbers greater than (2 " 2-23) x 2-128 are called _________.
A. negative underflow
B. positive overflow
C. positive underflow
D. negative overflow
"Memory is organized into records and access must be made in a specific linear
sequence" is a description of __________.
A. sequential access
B. direct access
C. random access
D. associative access
page-pf9
For the _________ mode, the operand is included in the instruction.
A. immediate
B. base
C. register
D. displacement
Replicating the entire processor on a single chip with each processor handling separate
threads is _________.
A. interleaved multithreading
B. blocked multithreading
C. simultaneous multithreading
D. chip multiprocessing
page-pfa
A _________ architecture is one that makes use of more, and more fine-grained
pipeline stages.
A. parallel
B. superpipelined
C. superscalar
D. hybrid
________ is a digital display interface standard now widely adopted for computer
monitors, laptop displays, and other graphics and video interfaces.
A. DisplayPort
B. PCI Express
C. Thunderbolt
D. InfiniBand
The I/O function includes a _________ requirement to coordinate the flow of traffic
between internal resources and external devices.
A. cycle
page-pfb
B. status reporting
C. control and timing
D. data
The GIC distributes interrupts to individual _________.
A. dies
B. cores
C. QPI
D. interconnects
__________ law deals with the potential speedup of a program using multiple
processors compared to a single processor.
A. Moore's
B. Amdahl's
C. Little's
D. Murphy's
page-pfc
A ________ hazard occurs when there is a conflict in the access of an operand location.
A. resource
B. data
C. structural
D. control
Binary 0101 is hexadecimal _________.
A. 0
B. 5
C. A
D. 10
page-pfd
The ________ portion of the control unit issues a repetitive sequence of pulses.
A. instruction register
B. flag
C. control bus signals
D. clock
Adjacent tracks are separated by _________.
A. sectors
B. gaps
C. pits
D. heads
Positive numbers less than 2-127 are called ________.
A. positive underflow
B. positive overflow
page-pfe
C. negative underflow
D. negative overflow
The ________ is connected to the data lines of the system bus.
A. MAR
B. PC
C. MBR
D. IR
Which of the following is a fundamental limitation to parallelism with which the system
must cope?
A. procedural dependency
B. resource conflicts
C. antidependency
D. all of the above
page-pff
The _________ stores data.
A. system bus
B. I/O
C. main memory
D. control unit
To enhance performance, a technique known as __________ is used for the shared L3
data cache.
A. cache banking
B. thread blocking
C. streaming
D. warping
page-pf10
Decimal "10" is __________ in binary.
A. 1000
B. 0010
C. 1010
D. 0001
With ________ instructions are simultaneously issued from multiple threads to the
execution units of a superscalar processor.
A. SMT
B. single-threaded scalar
C. coarse-grained multithreading
D. chip multiprocessing
A _________ is a special type of programming language used to provide instructions to
the monitor.
A. job control language
B. multiprogram
page-pf11
C. kernel
D. utility
A branch instruction in which the branch is always taken is _________.
A. conditional branch
B. unconditional branch
C. jump
D. bi-endian
A ________ is used to connect storage systems, routers, and other peripheral devices to
an InfiniBand switch.
A. target channel adapter
B. InfiniBand switch
C. host channel adapter
D. subnet
page-pf12
_________ is when multiple pipelines are constructed by replicating execution
resources, enabling parallel execution of instructions in parallel pipelines so long as
hazards are avoided.
A. Vectoring
B. Superscalar
C. Hybrid multithreading
D. Pipelining
A line includes a _________ that identifies which particular block is currently being
stored.
A. cache
B. hit
C. tag
D. locality
page-pf13
Three key interfaces in a typical computer system are: instruction set architecture,
application programming interface, and ___________.
The _________ Mean is preferred when calculating rates.
With multithreading the instruction stream is divided into several smaller streams,
known as threads, such that the threads can be executed in parallel.
The four states of the MESI protocol are: modified, shared, invalid, and ______.
page-pf14
A Thunderbolt compatible peripheral interface is no more complex than that of a simple
USB device.
Procedure calls and returns are not important aspects of HLL programs.
The ____________ generated by the control unit cause the opening and closing of logic
gates, resulting in the transfer of data to and from registers and the operation of the
ALU.
page-pf15
Microprogramming is the dominant technique for implementing control units in pure
_________ architectures due to its ease of implementation.
When using graph coloring, nodes that share the same color cannot be assigned to the
same register.
_________ states that performance increase is roughly proportional to square root of
increase in complexity.
_________ refers to the operational units and their interconnections that realize the
architectural specifications.
page-pf16
The __________ reference tells the processor where to fetch the next instruction after
the execution of this instruction is complete.
The __________ , or nucleus, contains the most frequently used functions in the OS.
Just as register addressing is analogous to direct addressing, ________ addressing is
analogous to indirect addressing.
page-pf17
The timing of processor operations is synchronized by the __________ and controlled
by the control unit with control signals.
The _________ connects multiple inputs to a single output.
A multipoint external interface provides a dedicated line between the I/O module and
the external device.
It is extremely easy to convert between binary and hexadecimal notation.
page-pf18
Data is organized on the platter in a concentric set of rings called ________.

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