CMCS 42882

subject Type Homework Help
subject Pages 5
subject Words 442
subject Authors William Stallings

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page-pf1
The term _________ parallelism refers to the degree to which, on average, the
instructions of a program can be executed in parallel.
The U.S. national version of the International Reference Alphabet is referred to as
__________.
The traditional __________ chip is constrained both by its internal architecture and by
its interface to the processor's memory bus.
In a traditional scalar organization there is a single pipelined functional unit for integer
operations and one for floating-point operations.
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A processor must: fetch instruction, interpret instruction, process data, write data, and
_________.
The focus of MMX technology is multimedia programming.
The principal disadvantage of a microprogrammed unit is that it will be somewhat
slower than a hardwired unit of comparable technology.
page-pf3
The fundamental building block of the Gen8 architecture is the ________ unit.
Computer systems that fall into the __________ category have a sequence of data that
is transmitted to a set of processors, each of which executes a different instruction
sequence.
On a movable-head system, the time it takes to position the head at the track is known
as __________.
__________ is a parallel computing platform and programming model created by
NVIDIA and implemented by the GPUs that they produce.
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At the most fundamental level, the speed of a processor is dictated by the pulse
frequency produced by the clock, measured in cycles per second, or _________.
Traditionally found on a plug-in graphics card, a _________ is used to encode and
render 2D and 3D graphics as well as process video.
Computer systems that fall into the __________ category have a single processor that
executes a single instruction stream to operate on data stored in a single memory.
page-pf5
__________ law deals with the potential speedup of a program using multiple
processors compared to a single processor.
__________ Law applies to a queuing system.
An I/O module must recognize one unique address for each peripheral it controls.

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