Exam
Name___________________________________
MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question.
1)
What advantage does a J–K flip–flop have over an R–S flip–flop?
1)
A)
It has fewer gates.
B)
It does not require a clock input.
C)
It has no invalid input states.
D)
It has only one output.
2)
A J–K flip–flop is being used as a divide–by–2 circuit when ________.
2)
A)
the reset is tied to the clock
B)
the J and K inputs are tied to ground
C)
the J and K inputs are tied to Vcc
D)
all the inputs are connected to the preset
3)
What primary advantage does the J–K flip–flop have over the S–R flip–flop?
3)
A)
The J–K flip–flop does not have an invalid input state.
B)
The J–K flip–flop does not have propagation delay problems.
C)
The J–K flip–flop is much faster.
D)
The J–K flip–flop only needs one output.
4)
What symbol is used to identify edge–triggered flip–flops?
4)
A)
A triangle on the Clock input
B)
An inverted “L” on the output
C)
The letter E on the Enable input
D)
A bubble on the Clock input
1
5)
Which of the following describes the operation of a positive edge–triggered D flip–flop?
5)
A)
The input is toggled into the flip–flop on the leading edge of the clock and is passed to the
output on the trailing edge of the clock.
B)
The output will follow the input on the leading edge of the clock.
C)
If both inputs are high, the output will toggle.
D)
When both inputs are low, an invalid state will exist.
6)
An astable multivibrator is a circuit that ________.
6)
A)
has two stable states
B)
has one stable state
C)
produces a continuous output signal
D)
Both B and C are correct.
7)
Which of the following is correct for a gated D latch?
7)
A)
The output complement follows the input when enabled.
B)
The output toggles if one of the inputs is held high.
C)
Q output follows the input D when the ENABLE is high.
D)
Only one of the inputs can be high at a time.
8)
If both inputs of an S–R flip–flop are low, what happens when the clock goes high?
8)
A)
No change occurs in the output.
B)
The output toggles.
C)
The output resets.
D)
An invalid state is produced.
9)
The asynchronous inputs to a flip–flop are normally labeled ________ and ________, and are
normally active ________ inputs.
9)
A)
START, STOP, low
B)
PRE, CLR, low
C)
ON, OFF, high
D)
SET, RESET, high
2
10)
Which of the following best describes the action of pulse–triggered flip–flops?
10)
A)
The data is entered on the leading edge of the clock, and transferred out on the trailing edge
of the clock.
B)
The synchronous inputs must be pulsed.
C)
The clock and R–S inputs must be pulse shaped.
D)
A pulse on the clock transfers data from input to output.
11)
Which of the following is a primary characteristic of the data lock–out flip–flop?
11)
A)
Data can only be entered when the clock is high.
B)
Data is only clocked into the FF on the clock transition.
C)
Data cannot be entered into the FF unless the EN line is high.
D)
The master section is a pulse triggered type FF.
B
12)
Pulse–triggered flip–flops are also called ________ flip–flops.
12)
A)
level
B)
edge
C)
master–slave
D)
postponed
C
13)
Flip–flops are normally used for all of the following applications, except ________.
13)
A)
logic gates
B)
frequency division
C)
data storage
D)
counting
A
14)
When both inputs of a J–K pulse–triggered FF are high, and the clock cycles, the output will
________.
14)
A)
toggle
B)
not change
C)
remain unchanged
D)
be invalid
A
3
A
15)
A positive edge–triggered J–K flip–flop is used to produce a two–phase clock. However, when the
circuit is operated it produces erratic results. Close examination with an oscilloscope reveals the
presence of glitches. What might be the source of these glitches?
15)
A)
A race condition exists between the Q and Q outputs to the AND gate.
B)
A race condition exists between the J and K inputs.
C)
A race condition exists between the CLOCK and the outputs of the flip–flop feeding the AND
gate.
D)
The PRESET and CLEAR terminals may have been left floating.
16)
An edge–triggered flip–flop must have ________.
16)
A)
at least two inputs to handle rising and falling edges
B)
a pulse transition detector
C)
active–low inputs and complemented outputs
D)
a very fast response time
17)
What is one disadvantage of an R–S flip–flop?
17)
A)
It has no Enable input.
B)
It has an invalid input state.
C)
It has only a single output.
D)
It has no CLOCK input.
18)
These waveforms are applied to a gated D latch, which is initially RESET. Which of the areas
identified on the Q waveform is incorrect?
18)
A)
Area a
B)
Area b
C)
Area c
D)
Area d
4
19)
Asynchronous inputs are best described as ________.
19)
A)
being tied to the clock, but not to the inputs
B)
having little or no control over the FF, except during the active clock input
C)
being tied to the inputs, but independent of the clock
D)
having full control over the FF, regardless of the input or clock states
20)
The L in 74L71 stands for ________.
20)
A)
lock–out flip–flop
B)
low frequency
C)
low power
D)
the type of package
21)
Which of the following ratings is not associated with flip–flops?
21)
A)
Set–up time
B)
Hold time
C)
Interval time
D)
Propagation delay time
22)
Set–up time specifies ________.
22)
A)
the minimum time required for the control levels to be maintained at the inputs of a flip–flop
prior to the triggering edge of the clock in order for data to be reliably clocked into the
component
B)
the maximum time interval required for the control levels to remain on the inputs before the
triggering edge of the clock in order for the data to be reliably clocked out of the FF
C)
how long it takes the output to change states after the clock has transitioned
D)
how long the operator has in order to get the flip–flop running before the maximum power
level is exceeded
5
23)
A push–button switch is used to input data to a register. The output of the register is erratic. Which
of the following could be the cause of the problem?
23)
A)
The register IC is intermittent and failure is imminent.
B)
The socket contacts on the register IC are corroded.
C)
The switch contacts are bouncing.
D)
The power supply is probably noisy.
24)
A retriggerable one–shot has a pulse width of 10 ms. Three milliseconds (3 ms) after being
triggered, another trigger pulse is applied. The duration of the resulting output pulse will be
________ ms.
24)
A)
10
B)
3
C)
7
D)
13
25)
A one–shot is classified as a(n) ________.
25)
A)
monostable multivibrator
B)
bistable multivibrator
C)
one–pulse multivibrator
D)
astable multivibrator
26)
An active–HIGH input S–R latch has a 1 on the S input and a 0 on the R input. What state is the
latch in?
26)
A)
Q = 0, Q= 1
B)
Q = 1, Q= 0
C)
Q = 1, Q= 1
D)
Q = 0, Q= 0
27)
How is the invalid input state problem associated with the S–R flip–flop overcome?
27)
A)
The R terminal is eliminated.
B)
A single input terminal is used (D).
C)
The R input is fed through an inverter.
D)
Both B and C are correct.
6
Explanation:
TRUE/FALSE. Write ‘T’ if the statement is true and ‘F’ if the statement is false.
28)
The J–K flip–flop toggles when both inputs are high during the transition of the clock signal.
28)
29)
Preset and Clear inputs are normally synchronous.
29)
30)
The ON time of a 555 monostable multivibrator is determined by tw= 1.1RC.
30)
31)
The 555 timer has three basic operating modes: monostable, bistable, and astable.
31)
32)
The symbol for an edge–triggered flip–flop has a triangle on its clock input.
32)
33)
A diode can be added to the discharge path for a 555 astable multivibrator to obtain duty cycles
that are less than 50%.
33)
34)
The waveforms for this J–K flip–flop indicate the circuit is operating properly.
34)
35)
A pulse–triggered flip–flop is identified by a bubble on its Q output terminal.
35)
36)
All multivibrators require feedback.
36)
7
37)
A D flip–flop is constructed by connecting an inverter between the Set and Clock terminals of a S–R
flip–flop.
37)
38)
All multivibrators are level triggered.
38)
39)
A one–shot is a multivibrator that must be triggered to produce each output pulse.
39)
40)
A J–K flip–flop can be used as a divide–by–two frequency divider with an output duty cycle of
50%.
40)
8
Answer Key
Testname: C7
9