Exam
Name___________________________________
MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question.
1)
An OLMC is an ________.
1)
A)
optical logic main communicator
B)
output logic macrocell
C)
output logic microcomputer
D)
onboard logic management controller
2)
For a GAL22V10, if the output from one pin is internally fed back to the input of another OLMC
then the propagation time of the second pin would ________.
2)
A)
decrease
B)
increase
C)
be unchanged
D)
cannot predict
3)
The main advantage of the V configuration such as a GAL22V10 is ________.
3)
A)
the output pins can be bi–directional
B)
the outputs can be configured as combinational or registered
C)
the outputs can be configured as active high or active low
D)
all of the above
4)
When tri–state outputs are used in a GAL22V10, ________.
4)
A)
multiple product terms can be used to control the output
B)
a single pin must be used for all tri–state control
C)
only one product term can be used to control the output
D)
all outputs must be controlled with the same control input
1
5)
Which Boolean Expressions are implemented by a PAL?
5)
A)
DeMorgan
B)
Product–of–Sum
C)
Sum–of–Product
D)
Both A and C
6)
The output logic macrocell in a GAL16V8 is ________.
6)
A)
internal to the GAL and can not be controlled
B)
only available when a pin is declared bi–directional
C)
the circuitry which allows the outputs to be configured as combinational or registered
D)
not used since the output pins are fixed
C
7)
A GAL16V8 has ________.
7)
A)
16 inputs and 8 variable outputs
B)
16 outputs and 8 inputs
C)
16 outputs and 8 variable inputs
D)
16 inputs and 8 inputs or outputs
A
8)
The part number PAL16H8 defines ________.
8)
A)
a PAL with 16 product matrix inputs and 8 active high, latched outputs
B)
a PLA with 16 matrix active high inputs and 8 outputs
C)
a PAL with 16 product matrix inputs and 8 active high outputs
D)
a PAL with 8 inputs and 16 active high outputs
C
9)
Why are the input variables to a PAL buffered?
9)
A)
To allow the input to be enabled
B)
To protect the inputs during programming of the PAL
C)
To prevent power drain when the inputs are not changing
D)
To prevent loading by a large number of AND gate inputs
D
2
C
10)
The main difference between a PAL and a GAL is ________.
10)
A)
a GAL can implement more complicated expressions than a PAL because it has more product
terms
B)
a GAL uses EECMOS technology and is re–programmable
C)
a PAL is designed for S0P equations while a GAL is designed for P0S
D)
a GAL has a programmable AND and OR matrix
TRUE/FALSE. Write ‘T’ if the statement is true and ‘F’ if the statement is false.
11)
The main difference between a GAL and a PAL is that the GAL is reprogrammable.
11)
12)
An FPGA (Field Programmable Gate Array) basically consists of an array of logic blocks with
programmable row and column interconnecting channels surrounded by programmable I/O
blocks.
12)
13)
A LUT can be programmed to perform logic functions.
13)
14)
A PAL has a programmable AND array and a programmable OR array.
14)
15)
SLPDs are the more complex form of PLDs.
15)
16)
A PAL can only be used for combinational logic.
16)
17)
An eight–wire JTAG compliant interface cable connects the computer running HDL software to the
SPLD already installed on a system circuit board.
17)
18)
A PAL16H8 has 16 active high output pins.
18)
3
19)
A typical FPGA logic element contains a 2–input LUT.
19)
20)
The file required to program a PAL is called a JEDEC file.
20)
21)
Programmable Logic Devices (PLDs) cannot be programmed by the user.
21)
22)
There is a limit to the number of product terms that can be assigned to each PAL output pin.
22)
23)
The GAL consists of a reprogrammable array of AND gates that connects to a fixed array of OR
gates.
23)
24)
All SPLD software and programmers (regardless of the manufacturer) utilize JEDEC files that
conform to established standards.
24)
25)
One advantage of PLDs over fixed–function logic devices is that many more logic circuits can be
packaged in a much smaller area.
25)
26)
A PLA has a higher propagation delay time than a PAL because the signal must traverse two
programmable arrays.
26)
27)
The typical EECMOS cell in a GAL will retain its programmed state for 5 to 10 years.
27)
28)
Input pins on PALs are buffered to allow both polarities of the input signal to be available to the
array.
28)
29)
When a PAL is programmed, small fuses are blown open to allow connections between the input
pins and the AND array.
29)
4
30)
The software packages for SPLD programming are called Logic Compilers.
30)
5
Answer Key
Testname: C10
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