While the processor is in user mode the program being executed is unable to access
protected system resources or to change mode, other than by causing an exception to
occur.
Program execution consists of repeating the process of instruction fetch and instruction
execution.
For the control unit to perform its function it must have inputs that allow it to determine
the state of the system and outputs that allow it to control the behavior of the system.
With asynchronous timing the occurrence of events on the bus is determined by a clock.
Superscalar execution is the same principle as seen in an assembly line.
A characteristic of ROM is that it is volatile.
A potential advantage to having only dedicate L2 caches on the chip is that each core
enjoys more rapid access to its private L2 cache.
With hybrid threading each major module is single threaded and the principal
coordination involves synchronizing all the threads with a timeline thread.
The allocation of control information between registers and memory are not considered
to be a key design issue.
True data dependency is also called flow dependency or read after write (RAW)
dependency.
The processor requires its own local memory.
The potential performance benefits of a multicore organization depend on the ability to
effectively exploit the parallel resources available to the application.
With demand paging it is necessary to load an entire process into main memory.
The end user is concerned mainly with the computer’s architecture.
The schedulers are responsible for retrieving micro-ops from the micro-op queues and
dispatching these for execution.
All of the Pentium processors include two on-chip L1 caches, one for data and one for
instructions.
The width of a track is double that of the head.
A common measure of performance for a processor is the rate at which instructions are
executed, expressed as millions of instructions per second (MIPS).
A computer is a complex system.
Condition codes facilitate multiway branches.
Both batch multiprogramming and time sharing use multiprogramming.
Resources include: memories, caches, buses, and register-file ports.
The IAS is the prototype of all subsequent general-purpose
computers.
The processor needs to store instructions and data temporarily while an instruction is
being executed.
An advantage of using a shared L2 cache on the chip is that data shared by multiple
cores is not replicated at the shared cache level.
One drawback of sign-magnitude representation is that there are two representations of
0.
At a top level, a computer consists of CPU, memory, and I/O components.
It has become possible to have a cache on the same chip as the processor.
Database management systems and database applications are one area in which
multicore systems can be used effectively.
The control unit is the engine that runs the entire computer.
Interrupt processing allows an application program to be suspended in order that a
variety of interrupt conditions can be serviced and later resumed.
Our primary counting system is based on binary digits to represent numbers.
Magnetic disks are the foundation of external memory on virtually all computer
systems.
The head must generate or sense an electromagnetic field of sufficient magnitude to
write and read properly.
Scheduling and memory management are the two OS functions that are most relevant to
the study of computer organization and architecture.
The two traditional forms of RAM used in computers are DRAM and SRAM.
RAID level 0 is not a true member of the RAID family because it does not include
redundancy to improve performance.
No single technology is optimal in satisfying the memory requirements for a computer
system.
The terms _________ microprogramming are used to suggest the degree of closeness to
the underlying control signals and hardware layout.
A. hard/soft
B. horizontal/vertical
C. direct/indirect
D. packed/unpacked
When the magnetizable coating is applied to both sides of the platter the disk is then
referred to as _________.
A. multiple sided
B. substrate
C. double sided
D. all of the above
A _________ accepts and/or transfers information serially.
A. S-R latch
B. shift register
C. FPGA
D. parallel register
Scanning information at the same rate by rotating the disk at a fixed speed is known as
the _________.
A. constant angular velocity
B. magnetoresistive
C. rotational delay
D. constant linear velocity
All MIPS R series processor instructions are encoded in a single ________ word
format.
A. 4-bit
B. 8-bit
C. 16-bit
D. 32-bit
The __________ performs the computer’s data processing functions.
A. Register
B. CPU interconnection
C. ALU
D. system bus
A measurement of how many tasks a computer can accomplish in a certain amount of
time is called a(n) __________ .
A. real-time system
B. application analysis
C. cycle speed
D. throughput
Another term for “base” is __________.
A. radix
B. integer
C. position
D. digit
________ indicates whether this micro-op is scheduled for execution, has been
dispatched for execution, or has completed execution and is ready for retirement.
A. State
B. Memory address
C. Micro-op
D. Alias register
__________ has the advantage of large address space, however it has the disadvantage
of multiple memory references.
A. Indirect addressing
B. Direct addressing
C. Immediate addressing
D. Stack addressing
The _________ exchanges data with the processor synchronized to an external clock
signal and running at the full speed of the processor/memory bus without imposing wait
states.
A. DDR-DRAM
B. SDRAM
C. CDRAM
D. none of the above
The unary operation _________ inverts the value of its operand.
A. OR
B. NOT
C. NAND
D. XOR
An instance of the kernel on the GPU is a ___________ .
A. thread
B. warp
C. grid
D. block
_________ provide storage internal to the CPU.
A. Control units
B. ALUs
C. Main memory
D. Registers
__________ involves the generation of partial products, one for each digit in the
multiplier, which are then summed to produce the final product.
A. Addition
B. Subtraction
C. Multiplication
D. Division
A _________ is a combinatorial circuit that generates an address based on the
microinstruction, the machine instruction, the microinstruction program counter, and an
interrupt register.
A. microsequencer
B. vertical microinstruction
C. translation array
D. control word
The _________ receives read and write requests from the software above the TL and
creates request packets for transmission to a destination via the link layer.
A. transaction layer
B. root layer
C. configuration layer
D. transport layer
The use of multiple processors on the same chip is referred to as __________ and
provides the potential to increase performance without increasing the clock rate.
A. multicore
B. GPU
C. data channels
D. MPC
A _________ is a collection of memory regions.
A. APX
B. nucleus
C. domain
D. page table
Negative numbers less than “(2 ” 2-23) x 2 128 are called _________.
A. positive underflow
B. positive overflow
C. negative underflow
D. negative overflow
A(n) __________ Mean is a good candidate for comparing the execution time
performance of several systems.
A. Composite
B. Arithmetic
C. Harmonic
D. Evaluation
__________ are characterized by the ability to support thousands of parallel execution
threads
A. CPUs
B. QPIs
C. GPUs
D. ISAs
The SDRAM performs best when it is transferring large blocks of data sequentially
such as for word processing, spreadsheets, and multimedia.
In most contemporary systems fixed-length sectors are used, with _________ bytes
being the nearly universal sector size.
A. 64
B. 128
C. 256
D. 512
The ________ contains I/O protocols that are mapped on to the transport layer.
A. cable
B. application
C. common transport
D. physical
Claude Shannon, a research assistant in the Electrical Engineering Department at
M.I.T., proposed the basic principles of Boolean algebra.
________ is used in scalar RISC processors to improve the performance of instructions
that require multiple cycles.
A. In-order completion
B. In-order issue
C. Out-of-order completion
D. Out-of-order issue
In 2006 NVIDIA facilitated the use of its new GPGPU language, ________ .
A. GPU/GP
B. SIMD
C. CUDA
D. NVIDIA C
The Pentium 4 _________ component executes micro-operations, fetching the required
data from the L1 data cache and temporarily storing results in registers.
A. fetch/decode unit
B. out-of-order execution logic
C. execution unit
D. memory subsystem
A subslice includes a unit called the _________, which is used for sampling texture and
image surfaces.
A. stride
B. sampler
C. EU
D. floating-point
The instructions following a branch have a _________ on the branch and cannot be
executed until the branch is executed.
A. resource dependency
B. procedural dependency
C. output dependency
D. true data dependency
A ________ is a dispatchable unit of work within a process that includes a processor
context and its own data area for a stack.
A. process
B. process switch
C. thread
D. thread switch
The _________ is an example of splitting off a separate, shared L3 cache, with
dedicated L1 and L2 caches for each core processor.
A. IBM 370
B. ARM11 MPCore
C. AMD Opteron
D. Intel Core i7
In the __________ mode the instruction includes a displacement to be added to a base
register, which may be any of the general-purpose registers.
An attractive feature of an SMP is that the existence of multiple processors is
transparent to the user.
_________ are bits in special registers that may be set by certain operations and used in
conditional branch instructions.
A _________, also known as a branch hazard, occurs when the pipeline makes the
wrong decision on a branch prediction and therefore brings instructions into the
pipeline that must subsequently be discarded.
A(n) __________ defines the layout of the bits of an instruction in terms of its
constituent fields, must include an opcode and, implicitly or explicitly, zero or more
operands.
The basic function of a computer is to execute programs.
Cache design for HPC is the same as that for other hardware platforms and applications.
The portion of the monitor that must always be in main memory and available for
execution is referred to as the __________.
A large number of general-purpose registers, and/or the use of compiler technology to
optimize register usage, a limited and simple instruction set, and an emphasis on
optimizing the instruction pipeline are all key elements of _________ architectures.
__________ works by creating resistance rather than directly storing charge.
Flash memory becomes unusable after a certain number of writes.
__________ is when the increment or decrement of the index register after each
reference to it is done automatically as part of the same instruction cycle.
The three key characteristics of memory are capacity, access time, and _______.
The __________ is the simplest mechanism for constructing a multiprocessor system.
Two key characteristics of a process are: scheduling/execution and ________.