Symmetric multiprocessors (SMPs) are one of the earliest, and still the most common,
example of parallel organization.
A(n) ________ interrupt is generated by an I/O controller to signal normal completion
of an operation, request service from the processor, or to signal a variety of error
conditions.
The _________ is a cache-coherent, point-to-point link based electrical interconnect
specification for Intel processors and chipsets that enable high-speed communications
among connected processor chips.
The major structural components of the CPU are: control unit, register, CPU
interconnection, and __________.
An approach that allows for a high degree of instruction-level parallelism without
increasing circuit complexity or power consumption is called ________.
An I/O module cannot exchange data directly with the processor.
When the processor, main memory, and I/O share a common bus, two modes of
addressing are possible: memory mapped and ________.
The simplest form of sequential circuit is the _________.
Widely used in data centers to save space and improve system management, a
_________ is a server architecture that houses multiple server modules in a single
chassis.
The _________ system has only two digits, 0 and 1.
“All instructions should have the “natural” number of operands” and “all operands
should have the same generality in specification” are two criteria that were used in
designing the __________ instruction format.
The principal building block of the IBM zEnterprise EC12 mainframe is the
__________ .
______ protocols distribute the responsibility for maintaining cache coherence among
all of the cache controllers in a multiprocessor.
In a __________ disk there is only one read-write head mounted on an arm that can be
extended or retracted to be able to be positioned above any track.
To ________ a signal is to cause a signal line to make a transition from its logically
false (0) state to its logically true (1) state.
An instruction cycle includes the following stages: fetch, execute, and _______.
Given ( . . . a3a2a1a0.a-1a-2a-3 . . . )r, the dot between a0 and a-1 is called the ________.
The _________ byte specifies whether an operand is in a register or in memory, and if it
is in memory, then fields within the byte specify the addressing mode to be used.
________ can improve performance by reducing loop overhead, increasing instruction
parallelism by improving pipeline performance, and improving register, data cache, or
TLB locality.
In __________ mode the I/O module and main memory exchange data directly, without
processor involvement.