Optical Audio Data Receiver
and Decoder
V1402
1
1. Overview
The V1402 decodes a single data stream of the industry–standard ADAT Optical protocol and produces four ADC
formats stereo pairs (8 channels) of digital audio suitable for DACs or further processing. With an internal PLL to
generate all needed clock signals, the V1402 requires no external clocks in Master Mode, and only word clock (Fs)
for proper operation in Slave Mode. The V1402 could be applied in digital mixing boards, signal processors and sound
reinforcement products, etc. V1402 features are:
• Compatible with ADAT Type I (16 bits), Type II (20 bits) and 24 bits formats
• 4 stereo pairs as outputs using standard ADC formats, supports both left and right justied data formats
• 4 IO bit outputs to receive timecode, MIDI data, S/Mux etc
• Internal PLL to generate all needed clock signals in Mater Mode
• Only word clock (Fs) for proper operation in Slave Mode
• Word clock input to synchronize outputs to user’s system
• Package: SOP24
2. Block Diagram and Pin Description
2 .1 Block Diagram
2.2 Block Description
The V1402 is consisted of chip reset, PLL3, PLL1, PLL2, ERR and output circuit. First to reset the chip before it start
to work, this will reset all internal counters and state registers to their initial state and disrupt the outputs. However,
PLL lock to OPIN will not be disturbed. V1402 has two work modes: Master Mode and Slave Mode. In Master Mode,
the V1402 requires no external clocks. All outputs are derived from the input ADAT Optical data stream on the OPIN
pin and WDCLK is an output signal. In Slave Mode, WDCLK is an input, OUT1/2-7/8, IO0–3, BCLK and SVCO are
synchronous to WDCLK. Output circuit transfers the serial data to 24–bit parallel data. 8 channels of 24–bit parallel data
are switched to 4 stereo pairs OUTPUT data and 4 IO data. When the V1402 lacks an input or failure to synchronize to
data stream occurs, ERR is high and data outputs are muted, but not clock outputs.